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ORCIDIsamu Hayashi
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2010 – 2019
- 2014
[c5]Koji Nii, Teruhiko Amano, Naoya Watanabe, Minoru Yamawaki, Kenji Yoshinaga, Mihoko Wada, Isamu Hayashi:
13.6 A 28nm 400MHz 4-parallel 1.6Gsearch/s 80Mb ternary CAM. ISSCC 2014: 240-241- 2013
- [j7]Isamu Hayashi, Teruhiko Amano, Naoya Watanabe, Yuji Yano, Yasuto Kuroda, M. Shirata, Katsumi Dosaka, Koji Nii, Hideyuki Noda, Hiroyuki Kawai:
A 250-MHz 18-Mb Full Ternary CAM With Low-Voltage Matchline Sensing Scheme in 65-nm CMOS. IEEE J. Solid State Circuits 48(11): 2671-2680 (2013) - 2012
- [c4]Takeshi Matsubara, Isamu Hayashi, Abul Hasan Johari, Tadahiro Kuroda, Hiroki Ishikuro:
A 0.7V 4.1mW 850Mbps/ch inductive-coupling transceiver with adaptive pulse width controller in 65nm CMOS. RWS 2012: 71-74 - 2010
- [c3]Abul Hasan Johari, Satoshi Kumaki, Takeshi Matsubara, Isamu Hayashi, Hiroki Ishikuro:
0.5 V multi-phase digital controlled oscillator with smooth phase transition circuit. APCCAS 2010: 232-235 - [c2]Satoshi Kumaki, Abul Hasan Johari, Takeshi Matsubara, Isamu Hayashi, Hiroki Ishikuro:
A 0.5V 6-bit scalable phase interpolator. APCCAS 2010: 1019-1022
2000 – 2009
- 2007
- [j6]Fukashi Morishita
, Hideyuki Noda, Isamu Hayashi, Takayuki Gyohten, Mako Okamoto, Takashi Ipposhi, Shigeto Maegawa, Katsumi Dosaka, Kazutami Arimoto:
A Capacitorless Twin-Transistor Random Access Memory (TTRAM) on SOI. IEICE Trans. Electron. 90-C(4): 765-771 (2007) - [j5]Fukashi Morishita, Isamu Hayashi, Takayuki Gyohten, Hideyuki Noda, Takashi Ipposhi, Hiroki Shimano, Katsumi Dosaka, Kazutami Arimoto:
A Configurable Enhanced TTRAM Macro for System-Level Power Management Unified Memory. IEEE J. Solid State Circuits 42(4): 853-861 (2007) - [j4]Kazutami Arimoto, Fukashi Morishita, Isamu Hayashi, Katsumi Dosaka, Hiroki Shimano, Takashi Ipposhi:
A High-Density Scalable Twin Transistor RAM (TTRAM) With Verify Control for SOI Platform Memory IPs. IEEE J. Solid State Circuits 42(11): 2611-2619 (2007) - 2006
- [j3]Takayuki Gyohten, Fukashi Morishita, Isamu Hayashi, Mako Okamoto, Hideyuki Noda, Katsumi Dosaka, Kazutami Arimoto, Yasutaka Horiba:
An On-Chip Supply-Voltage Control System Considering PVT Variations for Worst-Caseless Lower Voltage SoC Design. IEICE Trans. Electron. 89-C(11): 1519-1525 (2006) - [c1]Kazutami Arimoto, Fukashi Morishita, Isamu Hayashi, Tetsushi Tanizaki, Takashi Ipposhi, Katsumi Dosaka:
A Scalable ET2RAM (SETRAM) with Verify Control for SoC Platform Memory IP on SOI. CICC 2006: 429-432 - 2005
- [j2]Fukashi Morishita, Isamu Hayashi, Hideto Matsuoka, Kazuhiro Takahashi, Kuniyasu Shigeta, Takayuki Gyohten, Mitsutaka Niiro, Hideyuki Noda, Mako Okamoto, Atsushi Hachisuka, Atsushi Amo, Hiroki Shinkawata, Tatsuo Kasaoka, Katsumi Dosaka, Kazutami Arimoto, Kazuyasu Fujishima, Kenji Anami, Tsutomu Yoshihara:
A 312-MHz 16-Mb random-cycle embedded DRAM macro with a power-down data retention mode for mobile applications. IEEE J. Solid State Circuits 40(1): 204-212 (2005) - [j1]Hideyuki Noda, Kazunari Inoue, Masayuki Kuroiwa, Futoshi Igaue, Kouji Yamamoto, Hans Jürgen Mattausch, Tetsushi Koide, Atsushi Amo, Atsushi Hachisuka, Shinya Soeda, Isamu Hayashi, Fukashi Morishita, Katsumi Dosaka, Kazutami Arimoto, Kazuyasu Fujishima, Kenji Anami, Tsutomu Yoshihara:
A cost-efficient high-performance dynamic TCAM with pipelined hierarchical searching and shift redundancy architecture. IEEE J. Solid State Circuits 40(1): 245-253 (2005)
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