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2020 – today
- 2024
[j58]Aiwen Luo
, Sandip Bhattacharya, Mitiko Miura-Mattausch, Yicong Zhou, Hans Jürgen Mattausch:
Real-Time Surface Identification System for Variable Walking Speeds of Biped Robots. IEEE Embed. Syst. Lett. 16(2): 130-133 (2024)- 2022
- [j57]Tapas K. Maiti, Sunandan Dutta, Yoshihiro Ochi, Mitiko Miura-Mattausch, Hans Jürgen Mattausch:
Electro-mechanical Model and its Application to biped-robot stability with force Sensors. Int. J. Robotics Autom. 37(4) (2022) - 2021
- [j56]Abhishek Kar, Mitiko Miura-Mattausch, Mainak Sengupta, Dondee Navarro, Hideyuki Kikuchihara, Takahiro Iizuka, Hafizur Rahaman, Hans Jürgen Mattausch:
Simulation-Based Power-Loss Optimization of General-Purpose High-Voltage SiC MOSFET Circuit Under High-Frequency Operation. IEEE Access 9: 23786-23794 (2021) - [c58]Hideyuki Kikuchihara, Mitiko Miura-Mattausch, Takeshi Mizoguchi, Hajime Nagase, Makoto Hashimoto, Yusuke Kawaguchi, Hans Jürgen Mattausch:
Modeling of SJ-MOSFET for High-Voltage Applications with Inclusion of Carrier Dynamics during Switching. ISDCS 2021: 1-4 - [c57]Mitiko Miura-Mattausch, Hideyuki Kikuchihara, Hans Jürgen Mattausch:
Model Development for Robust Design of SOI-MOSFET Circuits used in Radiative Environments. ISDCS 2021: 1-4 - 2020
- [j55]Sandip Bhattacharya, Aiwen Luo, Sunandan Dutta, Mitiko Miura-Mattausch, Hans Jürgen Mattausch:
Force-Sensor-Based Surface Recognition With Surface-Property-Dependent Walking-Speed Adjustment of Humanoid Robot. IEEE Access 8: 169640-169651 (2020) - [j54]Sunandan Dutta, Tapas Kumar Maiti, Mitiko Miura-Mattausch, Yoshihiro Ochi, Naoto Yorino, Hans Jürgen Mattausch:
Analysis of Sensor-Based Real-Time Balancing of Humanoid Robots on Inclined Surfaces. IEEE Access 8: 212327-212338 (2020) - [j53]Sandip Bhattacharya, Sunandan Dutta, Aiwen Luo, Mitiko Miura-Mattausch, Yoshihiro Ochi, Hans Jürgen Mattausch:
Energy Efficiency of Force-Sensor-Controlled Humanoid-Robot Walking on Indoor Surfaces. IEEE Access 8: 227100-227112 (2020) - [j52]Kenshiro Sato, Dondee Navarro, Shinya Sekizaki, Yoshifumi Zoka, Naoto Yorino, Hans Jürgen Mattausch, Mitiko Miura-Mattausch:
Prediction of DC-AC Converter Efficiency Degradation due to Device Aging Using a Compact MOSFET-Aging Model. IEICE Trans. Electron. 103-C(3): 119-126 (2020) - [j51]Sunandan Dutta, Mitiko Miura-Mattausch, Yoshihiro Ochi, Naoto Yorino, Hans Jürgen Mattausch:
Gyro-Sensor-Based Vibration Control for Dynamic Humanoid-Robot Walking on Inclined Surfaces. Sensors 20(24): 7139 (2020) - [c56]Sandip Bhattacharya, Aiwen Luo, Sunandan Dutta, Mitiko Miura-Mattausch, Hans Jürgen Mattausch:
Surface Recognition and Speed Adjustment of Humanoid Robot Using External Control Circuit. ISDCS 2020: 1-4 - [c55]Soumajit Ghosh, Mitiko Miura-Mattausch, Takahiro Iizuka, Hideyuki Kikuchihara, Hafizur Rahaman, Hans Jürgen Mattausch:
History Effect on Circuit Performance of SOI-MOSFETs. ISDCS 2020: 1-5 - [c54]Fernando Ávila Herrera, Mitiko Miura-Mattausch, Takahiro Iizuka, Hideyuki Kikuchihara, Yoko Hirano, Hans Jürgen Mattausch:
Modeling of Short-Channel Effect on Multi-Gate MOSFETs for Circuit Simulation. ISDCS 2020: 1-4 - [c53]Hans Jürgen Mattausch, Aiwen Luo, Sunandan Dutta, Sunandan Dutta, Tapas K. Maiti, Mitiko Miura-Mattausch:
Force-Sensor-Based Walking-Environment Recognition of Biped Robots. ISDCS 2020: 1-4
2010 – 2019
- 2019
- [j50]Aiwen Luo, Fengwei An, Xiangyu Zhang, Hans Jürgen Mattausch:
A Hardware-Efficient Recognition Accelerator Using Haar-Like Feature and SVM Classifier. IEEE Access 7: 14472-14487 (2019) - [j49]Sandip Bhattacharya, Aiwen Luo, Tapas Kumar Maiti, Sunandan Dutta, Yoshihiro Ochi, Mitiko Miura-Mattausch, Hans Jürgen Mattausch:
Surface-Property Recognition With Force Sensors for Stable Walking of Humanoid Robot. IEEE Access 7: 146443-146456 (2019) - [j48]Arnab Mukhopadhyay, Tapas Kumar Maiti, Sandip Bhattacharya, Takahiro Iizuka, Hideyuki Kikuchihara, Mitiko Miura-Mattausch, Hafizur Rahaman, Sadayuki Yoshitomi, Dondee Navarro, Hans Jürgen Mattausch:
Prevention of Highly Power-Efficient Circuits due to Short-Channel Effects in MOSFETs. IEICE Trans. Electron. 102-C(6): 487-494 (2019) - [j47]Jungang Guan, Fengwei An, Xiangyu Zhang, Lei Chen, Hans Jürgen Mattausch:
Energy-Efficient Hardware Implementation of Road-Lane Detection Based on Hough Transform with Parallelized Voting Procedure and Local Maximum Algorithm. IEICE Trans. Inf. Syst. 102-D(6): 1171-1182 (2019) - [j46]Nezam Rohbani, Hiroaki Gau, Sara Mohammadinejad, Tapas Kumar Maiti, Dondee Navarro, Mitiko Miura-Mattausch, Hans Jürgen Mattausch, Hirotaka Takatsuka:
Power Reduction and BTI Mitigation of Data-Cache Memory Based on the Storage Management of Narrow-Width Values. IEEE Trans. Very Large Scale Integr. Syst. 27(7): 1675-1684 (2019) - [c52]Aiwen Luo, Sandip Bhattacharya, Tapas Kumar Maiti, Sunandan Dutta, Yoshihiro Ochi, Mitiko Miura-Mattausch, Hans Jürgen Mattausch:
Dynamic Pattern-Recognition-Based Walking-Speed Adjustment for Stable Biped-Robot Movement under Changing Surface Conditions. GCCE 2019: 600-601 - [c51]Nezam Rohbani, Tapas Kumar Maiti, Dondee Navarro, Mitiko Miura-Mattausch, Hans Jürgen Mattausch, Hirotaka Takatsuka:
NVDL-Cache: Narrow-Width Value Aware Variable Delay Low-Power Data Cache. ICCD 2019: 264-272 - [c50]Sunandan Dutta, Tapas K. Maiti, Yoshihiro Ochi, Mitiko Miura-Mattausch, Sandip Bhattacharya, Naoto Yorino, Hans Jürgen Mattausch:
Stability Analysis of Humanoid Robots with Gyro Sensors Subjected to External Push Forces. ISDCS 2019: 1-4 - [c49]Takahiro Iizuka, Hiroyuki Hashigami, Mitiko Miura-Mattausch, Hans Jürgen Mattausch:
Validation on Duality in Impact-ionization Carrier Generation at the Onset of Snapback in Power MOSFETs. ISDCS 2019: 1-4 - [c48]Tapas K. Maiti, Sunandan Dutta, Yoshihiro Ochi, Mitiko Miura-Mattausch, Sandip Bhattacharya, Hans Jürgen Mattausch:
Power Consumption Estimation of Biped Robot During Walking. ISDCS 2019: 1-4 - [c47]Yosuke Miyaoku, Mitiko Miura-Mattausch, Akihiro Tone, Hans Jürgen Mattausch, Kai Matsuura, Daisaku Ikoma:
Analysis of IGBT Charging/Discharging Mechanism for Accurate Compact Modeling. ISDCS 2019: 1-4 - [c46]Takao Yamamoto, Yukiya Fukunaga, Daisaku Ikoma, Mitiko Miura-Mattausch, Dondee Navarro, Hans Jürgen Mattausch:
Analysis of Embedded-Diode Performance in MOSFET under Switching Condition. ISDCS 2019: 1-4 - 2018
- [j45]Mitiko Miura-Mattausch, Hidenori Miyamoto, Hideyuki Kikuchihara, Tapas K. Maiti, Nezam Rohbani, Dondee Navarro, Hans Jürgen Mattausch:
Compact modeling of dynamic trap density evolution for predicting circuit-performance aging. Microelectron. Reliab. 80: 164-175 (2018) - [j44]Xiangyu Zhang, Fengwei An, Lei Chen, Idaku Ishii, Hans Jürgen Mattausch:
A Modular and Reconfigurable Pipeline Architecture for Learning Vector Quantization. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(10): 3312-3325 (2018) - [j43]Fengwei An, Xiangyu Zhang, Aiwen Luo, Lei Chen, Hans Jürgen Mattausch:
A Hardware Architecture for Cell-Based Feature-Extraction and Classification Using Dual-Feature Space. IEEE Trans. Circuits Syst. Video Technol. 28(10): 3086-3098 (2018) - [j42]Aiwen Luo, Fengwei An, Xiangyu Zhang, Lei Chen, Hans Jürgen Mattausch:
Resource-Efficient Object-Recognition Coprocessor With Parallel Processing of Multiple Scan Windows in 65-nm CMOS. IEEE Trans. Very Large Scale Integr. Syst. 26(3): 431-444 (2018) - [c45]Mitiko Miura-Mattausch, Hideyuki Kikuchihara, Tahahiro Kajiwara, Yuta Tanimoto, Atsushi Saito, Takahiro Iizuka, Dondee Navarro, Hans Jürgen Mattausch:
Compact Modeling for Power Efficient Circuit Design. ESSDERC 2018: 234-237 - [c44]Sandip Bhattacharya, Aiwen Luo, Tapas K. Maiti, Sunandan Dutta, Mitiko Miura-Mattausch, Hans Jürgen Mattausch:
Fast Recognition and Control of Walking Mode for Humanoid Robot Based on Pressure Sensors and Nearest Neighbor Search. ISPACS 2018: 331-334 - [c43]Sunandan Dutta, Tapas K. Maiti, Yoshihiro Ochi, Mitiko Miura-Mattausch, Sandip Bhattacharya, Dondee Navarro, Naoto Yorino, Hans Jürgen Mattausch:
Self-controlled walking robot with gyro sensor network for stable movement on non-smooth surfaces. SIMPAR 2018: 137-143 - 2017
- [j41]Takeshi Mizoguchi, Toshiyuki Naka, Yuta Tanimoto, Yasuhiro Okada, Wataru Saito, Mitiko Miura-Mattausch, Hans Jürgen Mattausch:
Modeling of Field-Plate Effect on Gallium-Nitride-Based High Electron Mobility Transistors for High-Power Applications. IEICE Trans. Electron. 100-C(3): 321-328 (2017) - [j40]Jungang Guan, Fengwei An, Xiangyu Zhang, Lei Chen, Hans Jürgen Mattausch:
Real-Time Straight-Line Detection for XGA-Size Videos by Hough Transform with Parallelized Voting Procedures. Sensors 17(2): 270 (2017) - [c42]Tapas K. Maiti, Dondee Navarro, Mitiko Miura-Mattausch, Hans Jürgen Mattausch:
Compact modeling approach for electro-mechanical system simulation. ASICON 2017: 981-984 - [c41]Mitiko Miura-Mattausch, Hidenori Miyamoto, Hideyuki Kikuchihara, Dondee Navarro, Tapas K. Maiti, Nezam Rohbani, C. Ma, Hans Jürgen Mattausch, A. Schiffmann, Alexander Steinmair, Ehrenfried Seebacher:
Modeling of dynamic trap density increase for aging simulation of any MOSFET circuits. ESSDERC 2017: 192-195 - 2016
- [j39]Fengwei An, Lei Chen, Toshinobu Akazawa, Shogo Yamazaki, Hans Jürgen Mattausch:
k Nearest Neighbor Classification Coprocessor with Weighted Clock-Mapping-Based Searching. IEICE Trans. Electron. 99-C(3): 397-403 (2016) - [j38]Lei Chen, Tapas Kumar Maiti, Hidenori Miyamoto, Mitiko Miura-Mattausch, Hans Jürgen Mattausch:
Actuator-Control Circuit Based on OTFTs and Flow-Rate Estimation for an All-Organic Fluid Pump. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 99-A(4): 798-805 (2016) - [j37]Atsushi Saito, Kenshiro Sato, Yuta Tanimoto, Kai Matsuura, Yutaka Sasaki, Mitiko Miura-Mattausch, Hans Jürgen Mattausch, Yoshifumi Zoka:
Efficiency Analysis of SiC-MOSFET-Based Bidirectional Isolated DC/DC Converters. IEICE Trans. Electron. 99-C(9): 1065-1070 (2016) - [j36]Fengwei An, Xiangyu Zhang, Lei Chen, Hans Jürgen Mattausch:
A Memory-Based Modular Architecture for SOM and LVQ with Dynamic Configuration. IEEE Trans. Multi Scale Comput. Syst. 2(4): 234-241 (2016) - [c40]Yuki Fujita, Fengwei An, Aiwen Luo, Xiangyu Zhang, Lei Chen, Hans Jürgen Mattausch:
Pixel-based pipeline hardware architecture for high-performance Haar-like feature extraction. APCCAS 2016: 611-612 - [c39]Fengwei An, Xiangyu Zhang, Lei Chen, Hans Jürgen Mattausch:
Dynamically reconfigurable system for LVQ-based on-chip learning and recognition. ISCAS 2016: 1338-1341 - 2015
- [c38]Fengwei An, Keisuke Mihara, Shogo Yamazaki, Lei Chen, Hans Jürgen Mattausch:
Word-parallel associative memory for k-nearest-neighbor with configurable storage space of reference vectors. A-SSCC 2015: 1-4 - [c37]Tapas Kumar Maiti, Lei Chen, Hidenori Miyamoto, Mitiko Miura-Mattausch, Hans Jürgen Mattausch:
Mixed-domain compact modeling framework for fluid flow driven by electrostatic organic actuators. ESSDERC 2015: 52-55 - 2014
- [j35]Indra Bagus Wicaksono, Fengwei An, Hans Jürgen Mattausch:
Memory-based hardware-accelerated system for high-speed human detection. Adv. Robotics 28(5): 317-327 (2014) - [j34]Takao Yamamoto, Masataka Miyake, Uwe Feldmann, Hans Jürgen Mattausch, Mitiko Miura-Mattausch:
Compact Modeling of Injection Enhanced Insulated Gate Bipolar Transistor Valid for Optimization of Switching Frequency. IEICE Trans. Electron. 97-C(10): 1021-1027 (2014) - [c36]Fengwei An, Toshinobu Akazawa, Shogo Yamazaki, Lei Chen, Hans Jürgen Mattausch:
LVQ neural network SoC adaptable to different on-chip learning and recognition applications. APCCAS 2014: 623-626 - [c35]Fengwei An, Toshinobu Akazawa, Shogo Yamazaki, Lei Chen, Hans Jürgen Mattausch:
A coprocessor for clock-mapping-based nearest Euclidean distance search with feature vector dimension adaptability. CICC 2014: 1-4 - [c34]Fengwei An, Lei Chen, Hans Jürgen Mattausch:
A SoPC architecture for nearest-neighbor based learning and recognition. ISPACS 2014: 147-152 - 2013
- [j33]Takahiro Iizuka, Kenji Fukushima, Akihiro Tanaka, Hideyuki Kikuchihara, Masataka Miyake, Hans Jürgen Mattausch, Mitiko Miura-Mattausch:
Modeling of Trench-Gate Type HV-MOSFETs for Circuit Simulation. IEICE Trans. Electron. 96-C(5): 744-751 (2013) - [j32]Chenyue Ma, Hans Jürgen Mattausch, Masataka Miyake, Takahiro Iizuka, Kazuya Matsuzawa, Seiichiro Yamaguchi, Teruhiko Hoshida, Akinori Kinoshita, Takahiko Arakawa, Jin He, Mitiko Miura-Mattausch:
Modeling of NBTI Stress Induced Hole-Trapping and Interface-State-Generation Mechanisms under a Wide Range of Bias Conditions. IEICE Trans. Electron. 96-C(10): 1339-1347 (2013) - [j31]Fengwei An, Hans Jürgen Mattausch:
K-means clustering algorithm for multimedia applications with flexible HW/SW co-design. J. Syst. Archit. 59(3): 155-164 (2013) - [c33]Toshinobu Akazawa, Seiryu Sasaki, Hans Jürgen Mattausch:
Word-parallel coprocessor architecture for digital nearest Euclidean distance search. ESSCIRC 2013: 267-270 - 2012
- [j30]Fengwei An, Tetsushi Koide, Hans Jürgen Mattausch:
A K-Means-Based Multi-Prototype High-Speed Learning System with FPGA-Implemented Coprocessor for 1-NN Searching. IEICE Trans. Inf. Syst. 95-D(9): 2327-2338 (2012) - [j29]Takahiro Iizuka, Takashi Sakuda, Yasunori Oritsuki, Akihiro Tanaka, Masataka Miyake, Hideyuki Kikuchihara, Uwe Feldmann, Hans Jürgen Mattausch, Mitiko Miura-Mattausch:
Compact Modeling of Expansion Effects in LDMOS. IEICE Trans. Electron. 95-C(11): 1817-1823 (2012) - [j28]Hans Jürgen Mattausch, Wataru Imafuku, Akio Kawabata, Tania Ansari, Masahiro Yasuda, Tetsushi Koide:
Associative Memory for Nearest-Hamming-Distance Search Based on Frequency Mapping. IEEE J. Solid State Circuits 47(6): 1448-1459 (2012) - [c32]Seiryu Sasaki, Masahiro Yasuda, Hans Jürgen Mattausch:
Digital associative memory for word-parrallel Manhattan-distance-based vector quantization. ESSCIRC 2012: 185-188 - [c31]Fengwei An, Hans Jürgen Mattausch:
Cluster-Based Prototype Learning System for Multiple Applications with Flexible HW/SW Codesign. PDCAT 2012: 416-419 - [c30]Indra Bagus Wicaksono, Fengwei An, Hans Jürgen Mattausch:
Human recognition with a hardware-accelerated multi-prototype learning and classification system. ROBIO 2012: 1507-1512 - 2011
- [j27]Ali Ahmadi, Hans Jürgen Mattausch, Md. Anwarul Abedin, Mahmoud Saeidi, Tetsushi Koide:
An associative memory-based learning model with an efficient hardware implementation in FPGA. Expert Syst. Appl. 38(4): 3499-3513 (2011) - [j26]Norio Sadachika, Shu Mimura, Akihiro Yumisaki, Koh Johguchi, Akihiro Kaya, Mitiko Miura-Mattausch, Hans Jürgen Mattausch:
Prediction of Circuit-Performance Variations from Technology Variations for Reliable 100 nm SOC Circuit Design. IEICE Trans. Electron. 94-C(3): 361-367 (2011) - [j25]Takeshi Kumaki, Tetsushi Koide, Hans Jürgen Mattausch, Masaharu Tagami, Masakatsu Ishizaki:
Software-Based Parallel Cryptographic Solution with Massive-Parallel Memory-Embedded SIMD Matrix Architecture for Data-Storage Systems. IEICE Trans. Inf. Syst. 94-D(9): 1742-1754 (2011) - [j24]Takashi Kurafuji, Masaru Haraguchi, Masami Nakajima, Tetsu Nishijima, Tetsushi Tanizaki, Hiroyuki Yamasaki, Takeaki Sugimura, Yuta Imai, Masakatsu Ishizaki, Takeshi Kumaki, Kan Murata, Kanako Yoshida, Eisuke Shimomura, Hideyuki Noda, Yoshihiro Okuno, Shunsuke Kamijo, Tetsushi Koide, Hans Jürgen Mattausch, Kazutami Arimoto:
A Scalable Massively Parallel Processor for Real-Time Image Processing. IEEE J. Solid State Circuits 46(10): 2363-2373 (2011) - [c29]Fengwei An, Hans Jürgen Mattausch, Tetsushi Koide:
Real-time hybrid learning and recognition system with software-hardware cooperation. ROBIO 2011: 2505-2510 - 2010
- [j23]Koh Johguchi, Akihiro Kaya, Shinya Izumi, Hans Jürgen Mattausch, Tetsushi Koide, Norio Sadachika:
Measurement-Based Ring Oscillator Variation Analysis. IEEE Des. Test Comput. 27(5): 6-13 (2010) - [c28]Hans Jürgen Mattausch, Wataru Imafuku, Tania Ansari, Akio Kawabata, Tetsushi Koide:
Low-power word-parallel nearest-Hamming-distance search circuit based on frequency mapping. ESSCIRC 2010: 538-541 - [c27]Akio Kawabata, Tetsushi Koide, Hans Jürgen Mattausch:
Optimization Vector Quantization by Adaptive Associative-Memory-Based Codebook Learning in Combination with Huffman Coding. ICNC 2010: 15-19 - [c26]Tetsushi Koide, R. Kimura, T. Sugahara, K. Okazaki, Hans Jürgen Mattausch:
Architecture and FPGA-Implementation of Scalable Picture Segmentation by 2D Scanning with Flexible Pixel-Block Size. ICNC 2010: 128-132 - [c25]Takashi Kurafuji, Masaru Haraguchi, Masami Nakajima, Takayuki Gyohten, Tetsu Nishijima, Hiroyuki Yamasaki, Yuta Imai, Masakatsu Ishizaki, Takeshi Kumaki, Yoshihiro Okuno, Tetsushi Koide, Hans Jürgen Mattausch, Kazutami Arimoto:
A scalable massively parallel processor for real-time image processing. ISSCC 2010: 334-335
2000 – 2009
- 2009
- [j22]Masataka Miyake, Daisuke Hori, Norio Sadachika, Uwe Feldmann, Mitiko Miura-Mattausch, Hans Jürgen Mattausch, Takahiro Iizuka, Kazuya Matsuzawa, Yasuyuki Sahara, Teruhiko Hoshida, Toshiro Tsukada:
Non-Quasi-Static Carrier Dynamics of MOSFETs under Low-Voltage Operation. IEICE Trans. Electron. 92-C(5): 608-615 (2009) - [j21]Masataka Miyake, Daisuke Hori, Norio Sadachika, Uwe Feldmann, Mitiko Miura-Mattausch, Hans Jürgen Mattausch, Tatsuya Ohguro, Takahiro Iizuka, Masahiko Taguchi, Shunsuke Miyamoto:
Degraded Frequency-Tuning Range and Oscillation Amplitude of LC-VCOs due to the Nonquasi-Static Effect in MOS Varactors. IEICE Trans. Electron. 92-C(6): 777-784 (2009) - 2008
- [b1]Mitiko Miura-Mattausch, Hans Jürgen Mattausch, Tatsuya Ezaki:
The Physics and Modeling of Mosfets - Surface-Potential Model HiSIM. International Series on Advances in Solid State Electronics and Technology, World Scientific 2008, ISBN 978-981-256-864-9, pp. 1-350 - [j20]Norio Sadachika, Takahiro Murakami, Hideki Oka, Ryou Tanabe, Hans Jürgen Mattausch, Mitiko Miura-Mattausch:
Compact Double-Gate Metal-Oxide-Semiconductor Field Effect Transistor Model for Device/Circuit Optimization. IEICE Trans. Electron. 91-C(8): 1379-1381 (2008) - [j19]Takeshi Kumaki, Masakatsu Ishizaki, Tetsushi Koide, Hans Jürgen Mattausch, Yasuto Kuroda, Takayuki Gyohten, Hideyuki Noda, Katsumi Dosaka, Kazutami Arimoto, Kazunori Saito:
Integration Architecture of Content Addressable Memory and Massive-Parallel Memory-Embedded SIMD Matrix for Versatile Multimedia Processor. IEICE Trans. Electron. 91-C(9): 1409-1418 (2008) - [j18]Tatsuya Ezaki, Dondee Navarro, Youichi Takeda, Norio Sadachika, Gaku Suzuki, Mitiko Miura-Mattausch, Hans Jürgen Mattausch, Tatsuya Ohguro, Takahiro Iizuka, Masahiko Taguchi, Shigetaka Kumashiro, Shunsuke Miyamoto:
Non-quasi-static approach with surface-potential-based MOSFET model HiSIM for RF circuit simulations. Math. Comput. Simul. 79(4): 1096-1106 (2008) - 2007
- [j17]Koh Johguchi, Yuya Mukuda, Ken-ichi Aoyama, Hans Jürgen Mattausch, Tetsushi Koide:
A 2-stage-pipelined 16 port SRAM with 590Gbps random access bandwidth and large noise margin. IEICE Electron. Express 4(2): 21-25 (2007) - [j16]Takeshi Kumaki, Yasuto Kuroda, Masakatsu Ishizaki, Tetsushi Koide, Hans Jürgen Mattausch, Hideyuki Noda, Katsumi Dosaka, Kazutami Arimoto, Kazunori Saito:
Real-Time Huffman Encoder with Pipelined CAM-Based Data Path and Code-Word-Table Optimizer. IEICE Trans. Inf. Syst. 90-D(1): 334-345 (2007) - [j15]Takeshi Kumaki, Yutaka Kono, Masakatsu Ishizaki, Tetsushi Koide, Hans Jürgen Mattausch:
Scalable FPGA/ASIC Implementation Architecture for Parallel Table-Lookup-Coding Using Multi-Ported Content Addressable Memory. IEICE Trans. Inf. Syst. 90-D(1): 346-354 (2007) - [j14]Md. Anwarul Abedin, Yuki Tanaka, Ali Ahmadi, Shogo Sakakibara, Tetsushi Koide, Hans Jürgen Mattausch:
Realization of K-Nearest-Matches Search Capability in Fully-Parallel Associative Memories. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 90-A(6): 1240-1243 (2007) - [j13]Takeshi Kumaki, Masakatsu Ishizaki, Tetsushi Koide, Hans Jürgen Mattausch, Yasuto Kuroda, Hideyuki Noda, Katsumi Dosaka, Kazutami Arimoto, Kazunori Saito:
Acceleration of DCT Processing with Massive-Parallel Memory-Embedded SIMD Matrix Processor. IEICE Trans. Inf. Syst. 90-D(8): 1312-1315 (2007) - [j12]Koh Johguchi, Hans Jürgen Mattausch, Tetsushi Koide, Tetsuo Hironaka:
4-Port Unified Data/Instruction Cache Design with Distributed Crossbar and Interleaved Cache-Line Words. IEICE Trans. Electron. 90-C(11): 2157-2160 (2007) - [c24]Koh Johguchi, Yuya Mukuda, Shinya Izumi, Hans Jürgen Mattausch, Tetsushi Koide:
A 0.6-Tbps, 16-port SRAM design with 2-stage- pipeline and multi-stage-sensing scheme. ESSCIRC 2007: 320-323 - [c23]Takeshi Kumaki, Tetsushi Koide, Hans Jürgen Mattausch, Yasuto Kuroda, Hideyuki Noda, Katsumi Dosaka, Kazutami Arimoto, Kazunori Saito:
Efficient Vertical/Horizontal-Space 1D-DCT Processing Based on Massive-Parallel Matrix-Processing Engine. ISCAS 2007: 525-528 - 2006
- [j11]Takashi Morimoto, Hidekazu Adachi, Osamu Kiriyama, Tetsushi Koide, Hans Jürgen Mattausch:
Boundary-Active-Only Adaptive Power-Reduction Scheme for Region-Growing Video-Segmentation. IEICE Trans. Inf. Syst. 89-D(3): 1299-1302 (2006) - [j10]Hideyuki Noda, Katsumi Dosaka, Hans Jürgen Mattausch, Tetsushi Koide, Fukashi Morishita, Kazutami Arimoto:
A Reliability-Enhanced TCAM Architecture with Associated Embedded DRAM and ECC. IEICE Trans. Electron. 89-C(11): 1612-1619 (2006) - [c22]Takashi Morimoto, Hidekazu Adachi, Kousuke Yamaoka, Kazutoshi Awane, Tetsushi Koide, Hans Jürgen Mattausch:
An FPGA-Based Region-Growing Video Segmentation System with Boundary-Scan-Only LSI Architecture. APCCAS 2006: 944-947 - [c21]Koh Johguchi, Zhaomin Zhu, Hans Jürgen Mattausch, Tetsushi Koide, Tetsuo Hironaka, Kazuya Tanigawa:
Unified Data/Instruction Cache with Hierarchical Multi-Port Architecture and Hidden Precharge Pipeline. APCCAS 2006: 1297-1300 - [c20]Md. Anwarul Abedin, Yuki Tanaka, Ali Ahmadi, Tetsushi Koide, Hans Jürgen Mattausch:
Fully Parallel Associative Memory Architecture with Mixed Digital-Analog Match Circuit for Nearest Euclidean Distance Search. APCCAS 2006: 1309-1312 - [c19]Takeshi Kumaki, Y. Kouno, Masakatsu Ishizaki, Tetsushi Koide, Hans Jürgen Mattausch:
Application of Multi-ported CAM for Parallel Coding. APCCAS 2006: 1859-1862 - [c18]Kousuke Yamaoka, Takashi Morimoto, Hidekazu Adachi, Tetsushi Koide, Hans Jürgen Mattausch:
Image segmentation and pattern matching based FPGA/ASIC implementation architecture of real-time object tracking. ASP-DAC 2006: 176-181 - [c17]Ali Ahmadi, M. Arifin Ritonga, Md. Anwarul Abedin, Hans Jürgen Mattausch, Tetsushi Koide:
A Learning OCR System Using Short/Long-term Memory Approach and Hardware Implementation in FPGA. IEEE Congress on Evolutionary Computation 2006: 687-693 - [c16]Kousuke Yamaoka, Takashi Morimoto, Hidekazu Adachi, Kazutoshi Awane, Tetsushi Koide, Hans Jürgen Mattausch:
Multi-object tracking VLSI architecture using image-scan based region growing and feature matching. ISCAS 2006 - 2005
- [j9]Shizunori Matsumoto, Hiroaki Ueno, Satoshi Hosokawa, Toshihiko Kitamura, Mitiko Miura-Mattausch, Hans Jürgen Mattausch, Tatsuya Ohguro, Shigetaka Kumashiro, Tetsuya Yamaguchi, Kyoji Yamashita, Noriaki Nakayama:
1/f-Noise Characteristics in 100 nm-MOSFETs and Its Modeling for Circuit Simulation. IEICE Trans. Electron. 88-C(2): 247-254 (2005) - [j8]Hideyuki Noda, Kazunari Inoue, Hans Jürgen Mattausch, Tetsushi Koide, Katsumi Dosaka, Kazutami Arimoto, Kazuyasu Fujishima, Kenji Anami, Tsutomu Yoshihara:
Embedded Low-Power Dynamic TCAM Architecture with Transparently Scheduled Refresh. IEICE Trans. Electron. 88-C(4): 622-629 (2005) - [j7]Dondee Navarro, Takeshi Mizoguchi, Masami Suetake, Kazuya Hisamitsu, Hiroaki Ueno, Mitiko Miura-Mattausch, Hans Jürgen Mattausch, Shigetaka Kumashiro, Tetsuya Yamaguchi, Kyoji Yamashita, Noriaki Nakayama:
A Compact Model of the Pinch-off Region of 100 nm MOSFETs Based on the Surface-Potential. IEICE Trans. Electron. 88-C(5): 1079-1086 (2005) - [j6]Kazunari Inoue, Hideyuki Noda, Kazutami Arimoto, Hans Jürgen Mattausch, Tetsushi Koide:
A CAM-Based Signature-Matching Co-processor with Application-Driven Power-Reduction Features. IEICE Trans. Electron. 88-C(6): 1332-1342 (2005) - [j5]Hideyuki Noda, Kazunari Inoue, Masayuki Kuroiwa, Futoshi Igaue, Kouji Yamamoto, Hans Jürgen Mattausch, Tetsushi Koide, Atsushi Amo, Atsushi Hachisuka, Shinya Soeda, Isamu Hayashi, Fukashi Morishita, Katsumi Dosaka, Kazutami Arimoto, Kazuyasu Fujishima, Kenji Anami, Tsutomu Yoshihara:
A cost-efficient high-performance dynamic TCAM with pipelined hierarchical searching and shift redundancy architecture. IEEE J. Solid State Circuits 40(1): 245-253 (2005) - [j4]Takahiro Sasaki, Tomohiro Inoue, Nobuhiko Omori, Tetsuo Hironaka, Hans Jürgen Mattausch, Tetsushi Koide:
Chip size and performance evaluations of shared cache for on-chip multiprocessor. Syst. Comput. Jpn. 36(9): 1-13 (2005) - [c15]Takashi Morimoto, Osamu Kiriyama, Hidekazu Adachi, Zhaomin Zhu, Tetsushi Koide, Hans Jürgen Mattausch:
A low-power video segmentation LSI with boundary-active-only architecture. ASP-DAC 2005: 13-14 - [c14]Ali Ahmadi, Md. Anwarul Abedin, Hans Jürgen Mattausch, Tetsushi Koide:
A parallel hardware design for parametric active contour models. AVSS 2005: 609-613 - [c13]Youichi Takeda, Dondee Navarro, Shingo Chiba, Mitiko Miura-Mattausch, Hans Jürgen Mattausch, Tatsuya Ohguro, Takahiro Iizuka, Masahiko Taguchi, Shigetaka Kumashiro, Shunsuke Miyamoto:
MOSFET harmonic distortion analysis up to the non-quasi-static frequency regime. CICC 2005: 827-830 - [c12]Takashi Morimoto, Osamu Kiriyama, Yohmei Harada, Hidekazu Adachi, Tetsushi Koide, Hans Jürgen Mattausch:
Object tracking in video pictures based on image segmentation and pattern matching. ISCAS (4) 2005: 3215-3218 - [c11]Tadashi Saito, Moto Maeda, Tetsuo Hironaka, Kazuya Tanigawa, Tetsuya Sueyoshi, Ken-ichi Aoyama, Tetsushi Koide, Hans Jürgen Mattausch:
Design of superscalar processor with multi-bank register file. ISCAS (4) 2005: 3507-3510 - [c10]Takeshi Kumaki, Yasuto Kuroda, Tetsushi Koide, Hans Jürgen Mattausch, Hideyuki Noda, Katsumi Dosaka, Kazutami Arimoto, Kazunori Saito:
CAM-based VLSI architecture for Huffman coding with real-time optimization of the code word table [image coding example]. ISCAS (5) 2005: 5202-5205 - 2004
- [j3]Takashi Morimoto, Yohmei Harada, Tetsushi Koide, Hans Jürgen Mattausch:
Efficient Video-Picture Segmentation Algorithm for Cell-Network-Based Digital CMOS Implementation. IEICE Trans. Inf. Syst. 87-D(2): 500-503 (2004) - [c9]Takashi Morimoto, Yohmei Harada, Tetsushi Koide, Hans Jürgen Mattausch:
350nm CMOS test-chip for architecture verification of real-time QVGA color-video segmentation at the 90nm technology node. ASP-DAC 2004: 531-532 - [c8]Yuji Yano, Tetsushi Koide, Hans Jürgen Mattausch:
Associative memory with fully parallel nearest-Manhattan-distance search for low-power real-time single-chip applications. ASP-DAC 2004: 543-544 - [c7]Tetsuya Sueyoshi, Hiroshi Uchida, Hans Jürgen Mattausch, Tetsushi Koide, Yosuke Mitani, Tetsuo Hironaka:
Compact 12-port multi-bank register file test-chip in 0.35µm CMOS for highly parallel processors. ASP-DAC 2004: 551-552 - 2003
- [c6]Kazuya Hisamitsu, Hiroaki Ueno, Masayasu Tanaka, Daisuke Kitamaru, Mitiko Miura-Mattausch, Hans Jürgen Mattausch, Shigetaka Kumashiro, Tetsuya Yamaguchi, Kyoji Yamashita, Noriaki Nakayama:
Temperature-independence-point properties for 0.1μm-scale pocket-implant technologies and the impact on circuit design. ASP-DAC 2003: 179-183 - [c5]Tetsushi Koide, Hans Jürgen Mattausch, Yuji Yano, Takayuki Gyohten, Yoshihiro Soda:
A nearest-hamming-distance search memory with fully parallel mixed digital-analog match circuitry. ASP-DAC 2003: 591-592 - [c4]Zhaomin Zhu, Koh Johguchi, Hans Jürgen Mattausch, Tetsushi Koide, Tai Hirakawa, Tetsuo Hironaka:
A novel hierarchical multi-port cache. ESSCIRC 2003: 405-408 - 2002
- [j2]Mitiko Miura-Mattausch, Hiroaki Ueno, Hans Jürgen Mattausch, Shigetaka Kumashiro, Tetsuya Yamaguchi, Kyoji Yamashita, Noriaki Nakayama:
Circuit Simulation Models for Coming MOSFET Generations. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 85-A(4): 740-748 (2002) - [j1]Hans Jürgen Mattausch, Takayuki Gyohten, Yoshihiro Soda, Tetsushi Koide:
Compact associative-memory architecture with fully parallel search capability for the minimum Hamming distance. IEEE J. Solid State Circuits 37(2): 218-227 (2002) - 2001
- [c3]D. Miyawaki, Shizunori Matsumoto, Hans Jürgen Mattausch, S. Ooshiro, Masami Suetake, Mitiko Miura-Mattausch, Shigetaka Kumashiro, Tetsuya Yamaguchi, Kyoji Yamashita, Noriaki Nakayama:
Correlation method of circuit-performance and technology fluctuations for improved design reliability. ASP-DAC 2001: 39-44 - [c2]Shizunori Matsumoto, Hans Jürgen Mattausch, S. Ooshiro, Y. Tatsumi, Mitiko Miura-Mattausch, Shigetaka Kumashiro, Terufumi Yamaguchi, Kyoji Yamashita, Noriaki Nakayama:
Test-circuit-based extraction of inter- and intra-chip MOSFET-performance variations for analog-design reliability. CICC 2001: 357-360 - 2000
- [c1]Masayasu Tanaka, N. Tokida, T. Okagaki, Mitiko Miura-Mattausch, Walter Hansch, Hans Jürgen Mattausch:
High performance of short-channel MOSFETs due to an elevated central-channel doping. ASP-DAC 2000: 365-370
Coauthor Index
Tapas K. Maiti
aka: Tapas Kumar Maiti
aka: Tapas Kumar Maiti
[j58] [j57] [j56] [c58] [c57] [j55] [j54] [j53] [j52] [j51] [c56] [c55] [c54] [c53] [j49] [j48] [j46] [c52] [c51] [c50] [c49] [c48] [c47] [c46] [j45] [c45] [c44] [c43] [j41] [c42] [c41] [j38] [j37] [c37] [j34] [j33] [j32] [j29] [j26] [j22] [j21] [b1] [j20] [j18] [j9] [j7] [c13] [c6] [j2] [c3] [c2] [c1]
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