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ORCIDCICC 2006: San Jose, California, USA
- Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, CICC 2006, DoubleTree Hotel, San Jose, California, USA, September 10-13, 2006. IEEE 2006, ISBN 1-4244-0075-9
- Lalitha Mohana Kalyani-Garimella, Annajirao Garimella, Jaime Ramírez-Angulo, Ramón González Carvajal
, Antonio J. López-Martín:
Low-Voltage Universal Cell (LVUC): A Compact Analog/Digital Logic Block for Mixed Signal FPGAs. 1-4 - Christopher M. Twigg, Paul E. Hasler:
A Large-Scale Reconfigurable Analog Signal Processor (RASP) IC. 5-8 - Arifur Rahman, Satyaki Das, Tim Tuan, Steven Trimberger:
Determination of Power Gating Granularity for FPGA Fabric. 9-12 - Rajit Manohar:
Reconfigurable Asynchronous Logic. 13-20 - Changhua Cao, Yanping Ding, Kenneth K. O:
A 50-GHz Phase-Locked Loop in 130-nm CMOS. 21-24 - Antonio Liscidini, Cesare Ghezzi, Emanuele Depaoli, Guido Albasini, Ivan Bietti, Rinaldo Castello:
Common Gate Transformer Feedback LNA in a High IIP3 Current Mode RF CMOS Front-End. 25-28 - William F. Andress, David S. Ricketts, Xiaofeng Li, Donhee Ham:
Passive & Active Control of Regenerative Standing & Soliton Waves. 29-36 - Hui Zheng, Howard C. Luong:
A 0.9-V Double-Balanced Quadrature-Input Quadrature-Output Frequency Divider. 37-40 - János Márkus, Philippe Deval, Vincent Quiquempoix, José B. Silva, Gabor C. Temes:
Incremental Delta-Sigma Structures for DC Measurement: an Overview. 41-48 - Zhiheng Cao, Tongyu Song, Shouli Yan:
A 14mW 2.5MS/s 14bit Sigma-Delta Modulator Using Pseudo-Differential Split-Path Cascode Amplifiers. 49-52 - Yusuke Kanazawa, Yoshihisa Fujimoto, Pascal Lo Ré, Masayuki Miyamoto:
A 100-MS/s 4-MHz Bandwidth 77.3-dB SNDR ΔΣ ADC with a Triple Sampling Technique. 53-56 - Tongyu Song, Zhiheng Cao, Shouli Yan:
A 2.7mW 2MHz Continuous-Time ΣΔ Modulator with a Hybrid Active-Passive Loop Filter. 57-60 - Mona Safi-Harb, Gordon W. Roberts:
A 70-GHz Effective Sampling Rate On-Chip Oscilloscope with Time-Domain Digitization. 61-64 - Mike Peng Li:
Jitter And Signaling Test For High-Speed Links. 65-72 - Shanthi Pavan, Tonse Laxminidhi:
A Technique for Accurate Frequency Response Measurement of Integrated Continuous-Time Filters. 77-80 - Robert Bogdan Staszewski, Tom Jung, Roman Staszewski, Khurram Muhammad, Dirk Leipold, Thomas Murphy, S. Sabin, John L. Wallberg, S. Larson, Mitch Entezari, J. Fresquez, S. Dondershine, S. Syed:
Software Assisted Digital RF Processor for Single-Chip GSM Radio in 90 nm CMOS. 81-84 - Chunlei Shi, Brett C. Walker, Eric Zeisel, Brian Hu, Gene H. McAllister:
A Highly Integrated Power Management IC for Advanced Mobile Applications. 85-88 - Alireza Shirvani, Derek Cheung, Randy Tsang, Shafiq Jamal, Thomas Cho, Xiaodong Jin, Yonghua Song:
A dual-band triple-mode SoC for 802.11a/b/g Embedded WLAN in 90nm CMOS. 89-92 - Massimo Bocchi, Mario de Dominicis, Claudio Mucci, Antonio Deledda, Fabio Campi, Andrea Lodi, Mario Toma, Roberto Guerrieri:
Design and implementation of a reconfigurable heterogeneous multiprocessor SoC. 93-96 - Rakesh H. Patel, William Bereza:
Embedded Mixed-Signal IP Development Methodology in 90nm CMOS SerDes FPGAs. 97-100 - K. Venkataraman, V. Suresh, S. Iyengar, M. Ott, S. R. Kalari, J. Zhi, E. Ruetz, M. Gray, B. Reynov, A. Iqbal:
Integrated 155M-10Gbps Framer with 22.5Gbps Low/High Order Cross Connect SoC. 101-104 - Jim Le, Christopher Hanken, Martin Held, Michael S. Hagedorn, Kartikeya Mayaram, Terri S. Fiez:
Comparison and Impact of Substrate Noise Generated by Clocked and Clockless Digital Circuitry. 105-108 - Sungdae Choi, Seong-Jun Song, Kyomin Sohn, Hyejung Kim, Joo-Young Kim, Namjun Cho, Jeong-Ho Woo, Jerald Yoo, Hoi-Jun Yoo:
A Multi-Nodes Human Body Communication Sensor Network Control Processor. 109-112 - David Su:
Challenges in Designing Low-Power CMOS Wireless Systems-on-a-Chip. 113-120 - S. Beyer, R. Jaehne, W. Kluge, D. Eggert:
A 2.4GHz direct modulated 0.18μm CMOS IEEE 802.15.4 compliant Transmitter for ZigBee. 121-124 - Albert C. Jerng, Charles G. Sodini:
A Wideband ΔΣ Digital-RF Modulator With Self-Tuned RF Bandpass Reconstruction Filter. 125-128 - Siray Akhtar, Mehmet Ipek, J. Lin, Robert Bogdan Staszewski, Petteri Litmanen:
Quad Band Digitally Controlled Oscillator for WCDMA Transmitter in 90nm CMOS. 129-132 - Luigi Panseri, Luca Romanò, Salvatore Levantino, Carlo Samori, Andrea L. Lacaita:
Low-power CMOS IEEE 802.11a/g Signal Separator for Outphasing Transmitter. 133-136 - Amin Shameli, Aminghasem Safarian, Ahmadreza Rofougaran, Maryam Rofougaran, Franco De Flaviis:
A Novel DAC Based Switching Power Amplifier for Polar Transmitter. 137-140 - Gang Liu, Tsu-Jae King Liu, Ali M. Niknejad:
A 1.2V, 2.4GHz Fully Integrated Linear CMOS Power Amplifier with Efficiency Enhancement. 141-144 - Yong-Hee Lee, Moo-Yeol Choi, Seung-Bin You, Wang-Seup Yeum, Ho-Jin Park, Jae-Whui Kim:
A 4mW per-Channel 101dB-DR Stereo Audio DAC with Transformed Quantization Structure. 145-148 - Erhan Ozalevli, Hüseyin Dinc, Haw-Jing Lo, Paul E. Hasler:
Design of a binary-weighted resistor DAC using tunable linearized floating-gate CMOS resistors. 149-152 - Douglas A. Mercer:
Low Power Approaches to High Speed CMOS Current Steering DACs. 153-160 - Babak Nejati, Lawrence Larson:
An Area Optimized 2.5-V 10-b 200-MS/s 200-μA CMOS DAC. 161-164 - Jing Cao, Haiqing Lin, Yihai Xiang, Chungpao Kao, Ken Dyer:
A 10-bit 1GSample/s DAC in 90nm CMOS for Embedded Applications. 165-168 - Patrick G. Drennan, M. L. Kniffin, D. R. Locascio:
Implications of Proximity Effects for Analog Design. 169-176 - Kenneth S. Kundert, Henry Chang:
Verification of Complex Analog Integrated Circuits. 177-184 - Saurabh K. Tiwary, Rob A. Rutenbar:
On-the-Fly Fidelity Assessment for Trajectory-Based Circuit Macromodels. 185-188 - Sarvesh Bhardwaj, Wenping Wang, Rakesh Vattikonda, Yu Cao, Sarma B. K. Vrudhula:
Predictive Modeling of the NBTI Effect for Reliable Design. 189-192 - Christoph Hagleitner, Anthony R. Bonaccio, Hugo E. Rothuizen, Dorothea Wiesmann, Jan Lienemann, Jan G. Korvink, Giovanni Cherubini, Evangelos Eleftheriou:
Modeling, Design, and Verification for the Analog Front-end of a MEMS-based Parallel Scanning-probe Storage Device. 193-196 - Khaled Abdelfattah, Behzad Razavi:
Modeling Op Amp Nonlinearity in Switched-Capacitor Sigma-Delta Modulators. 197-200 - Murali Shanmugasundaram, Shanthi Pavan:
Rapid Simulation of Current Steering Digital-to-Analog Converters using Verilog-A. 201-204 - Mohammad Sharifkhani, Manoj Sachdev:
A Phase-Domain Continuous-Time 2nd-Order ΔΣ Frequency Digitizer. 205-208 - Zwei-Mei Lee, Cheng-Yeh Wang, Jieh-Tsorng Wu:
A CMOS 15-Bit 125-MS/s Time-Interleaved ADC with Digital Background Calibration. 209-212 - Wonseok Oh, Bertan Bakkaloglu, Bhaskar Aravind, Siew Kuok Hoon:
A Low 1/f Noise CMOS Low-Dropout Regulator with Current-Mode Feedback Buffer Amplifier. 213-216 - Kamal El-Sankary, Mohamad Sawan:
10-b 100-MS/s Two-Channel Time-Interleaved Pipelined ADC. 217-220 - Xiangtao Li, Wei-Min Lance Kuo, Yuan Lu, John D. Cressler:
A 20 GS/sec Analog-to-Digital Sigma-Delta Modulator in SiGe HBT Technology. 221-224 - Xinyu Yu, Steven L. Garverick:
A 300 °C, 110-dB Sigma-Delta Modulator with Programmable Gain in Bulk CMOS. 225-228 - Sam Kavusi, Kunal Ghosh, Keith Fife, Abbas El Gamal:
A 0.18μm CMOS 1000 frames/sec, 138dB Dynamic Range Readout Circuit for 3D-IC IR Focal Plane Arrays. 229-232 - Ashkan Olyaei, Roman Genov:
ViPro: Focal-Plane Spatially-Oversampling CMOS Image Compression Sensor. 233-236 - Thomas William Brown, Terri S. Fiez, Mikko Hakkarainen:
Prediction and Characterization of Frequency Dependent MOS Switch Linearity and the Design Implications. 237-240 - Martin Hansson, Behzad Mesgarzadeh, Atila Alvandpour:
1.56 GHz On-chip Resonant Clocking in 130nm CMOS. 241-244 - Mohankumar N. Somasundaram, Dongsheng Ma:
Low-Ripple CMOS Switched-Capacitor Power Converter With Closed-Loop Interleaving Regulation. 245-248 - Hong Yu, Rizwan Bashirullah:
A Low Power ASK Clock and Data Recovery Circuit for Wireless Implantable Electronics. 249-252 - Janghoon Song, Gilwon Yoon, Chulwoo Kim:
An Efficient Adaptive Digital DC-DC Converter with Dual Loop Controls for Fast Dynamic Voltage Scaling. 253-256 - Sheng-Yu Peng, Muhammad Shakeel Qureshi, Arindam Basu, Paul E. Hasler, Levent Degertekin:
A Floating-gate Based Low-Power Capacitive Sensing Interface Circuit. 257-260 - Andrew W. Howard, Gu-Yeon Wei, William J. Dally, Paul Horowitz:
Pulsenet - A Parallel Flash Sampler and Digital Processor IC for Optical SETI. 261-264 - Liang Zhang, John M. Wilson, Rizwan Bashirullah, Lei Luo, Jian Xu, Paul D. Franzon:
A 32Gb/s On-chip Bus with Driver Pre-emphasis Signaling. 265-268 - Ye-Ming Li, Robert Wodnicki, Naveen Chandra, Naresh Rao:
An Integrated 90V Switch Array for Medical Ultrasound Applications. 269-272 - Kea-Tiong Tang, Rodney M. Goodman:
Towards a Wearable Electronic Nose Chip. 273-276 - Edward K. F. Lee, Eusebiu Matei, Anthony Lam, Taihu Li:
A 1V 420μW 32-channel Cortical Signal Interface. 277-280 - Keith Fife, Abbas El Gamal, H.-S. Philip Wong:
A 3D Multi-Aperture Image Sensor Architecture. 281-284 - Vladimir I. Prodanov, Mihai Banu:
GHz Serial Passive Clock Distribution in VLSI Using Bidirectional Signaling. 285-288 - Shahin Jafarabadi-Ashtiani, Arokia Nathan:
A Driving Scheme for AMOLED Displays Based on Current Feedback. 289-292 - Triet Le, Kartikeya Mayaram, Terri S. Fiez:
Efficient Far-Field Radio Frequency Power Conversion System for Passively Powered Sensor Networks. 293-296 - Nitin Mohan, Wilson Fung, Derek Wright, Manoj Sachdev:
Match Line Sense Amplifiers with Positive Feedback for Low-Power Content Addressable Memories. 297-300 - Kostas Pagiamtzis, Navid Azizi, Farid N. Najm:
A Soft-Error Tolerant Content-Addressable Memory (CAM) Using An Error-Correcting-Match Scheme. 301-304 - Liyang Pan, Dong Wu, Guangjun Yang, Lei Sun, Huiqing Pang, Jun Zhu:
180nm 4Mb High Speed High Reliability Embedded SONOS Flash Memory. 305-308 - Luca Ciccarelli, Domenico Loparco, Massimiliano Innocenti, Andrea Lodi, Claudio Mucci, Pier Luigi Rolandi:
A Low-Power Routing Architecture Optimized for Deep Sub-Micron FPGAs. 309-312 - Giby Samson, Lawrence T. Clark:
A 0.13 μm Low-power Race-free Programmable Logic Array. 313-316 - Liping Guo, Mackenzie R. Scott, Rajeevan Amirtharajah:
An Energy Scalable Computational Array for Sensor Signal Processing. 317-320 - Sizhong Chen, Fei Sun, Tong Zhang:
Nonlinear Soft-Output Signal Detector Design and Implementation for MIMO Communication Systems with High Spectral Efficiency. 321-324 - Hao Zhong, Tong Zhang, Erich F. Haratsch:
VLSI Design of High-Rate Quasi-Cyclic LDPC Codes for Magnetic Recording Channel. 325-328 - Shoushun Chen, Amine Bermak, Wang Yan, Dominique Martinez:
A CMOS Image Sensor with combined adaptive-quantization and QTD-based on-chip compression processor. 329-332 - George Suárez Martínez, Manuel Jiménez-Cedeño:
Considerations for Accurate Behavioral Modeling of High-Speed SC ΣΔ Modulators. 333-336 - Jie Gu, John Keane, Sachin S. Sapatnekar, Chris H. Kim:
Width Quantization Aware FinFET Circuit Design. 337-340 - Takafumi Yamamoto, Tsutomu Suzuki, Hideki Asai:
Concurrent Design of Delta-Sigma Modulator Using Behavioral Modeling and Simulation with the Verilog-A. 341-344 - Vishal Bhargava, N. Haider, N. Sarpotdar:
IO Clock Network Skew & Performance Analysis: A Pentium-D Case Study. 345-348 - Shweta Srivastava, Xiaolue Lai, Jaijeet S. Roychowdhury:
Nonlinear Phase Macromodel Based Simulation/Design of PLLs with Superharmonically Locked Dividers. 349-352 - Chun-Jung Chen, Tai-Ning Yang, Jenn-Dong Sun:
The Backward-traversing Relaxation Algorithm for Circuit Simulation. 353-356 - Patrick P. Mercier, S. R. Singh, Krzysztof Iniewski, Brian Moore, P. O'Shea:
Yield and Cost Modeling for 3D Chip Stack Technologies. 357-360 - Ming-Dou Ker, Cheng-Cheng Yen, Pi-Chia Shih:
On-Chip Transient Detection Circuit for System-Level ESD Protection in CMOS ICs. 361-364 - Daeik D. Kim, Choongyeun Cho, Jonghae Kim, Jean-Olivier Plouchart, Robert Trzcinski, David Ahlgren:
CMOS Mixed-Signal Circuit Process Variation Sensitivity Characterization for Yield Improvement. 365-368 - Mizuki Motoyoshi, Minoru Fujishima:
In Situ Evaluation Method for On-Chip Inductors Using Oscillator Response. 369-372 - Toshiya Mitomo, Osamu Watanabe, Ryuichi Fujimoto, Shunji Kawaguchi:
A Quadrature Demodulator for WCDMA Receiver Using Common-Base Input Stage with Robustness to Transmitter Leakage. 373-376 - Ja-Yol Lee, Kwi-Dong Kim, Jong-Kee Kwon, Seung-Chul Lee, Jongdae Kim, Sang-Heung Lee:
A 3.8-5.5-GHz Multi-Band CMOS Frequency Synthesizer for WPAN/WLAN Applications. 377-380 - Harish Krishnaswamy, Hossein Hashemi:
Inductor- and Transformer-based Integrated RF Oscillators: A Comparative Study. 381-384 - Karan S. Bhatia, Sami Hyvonen, Elyse Rosenbaum:
An 8-mW, ESD-protected, CMOS LNA for Ultra-Wideband Applications. 385-388 - Bagher Afshar, Ali M. Niknejad:
X/Ku Band CMOS LNA Design Techniques. 389-392 - Sayf Alalusi, Robert W. Brodersen:
A 60GHz Phased Array in CMOS. 393-396 - Chihun Lee, Lan-chou Cho, Shen-Iuan Liu:
A 44GHz Dual-Modulus Divide-by-4/5 Prescaler in 90nm CMOS Technology. 397-400 - David A. Yokoyama-Martin, Kannan Krishna, John T. Stonick, Aaron Caffee, E. K. Gamble, Chris Jones, J. Mcneal, James Parker, Ross Segelken, Jeff L. Sonntag, K. Umino, J. Upton, Daniel Weinlader, Skye Wolfer:
A Multi-Standard Low Power 1.5-3.125 Gb/s Serial Transceiver in 90nm CMOS. 401-404 - Kin-Joe Sham, Mahmoud Reza Ahmadi, S. B. Gerry Talbot, Ramesh Harjani:
FEXT Crosstalk Cancellation for High-Speed Serial Link Design. 405-408 - Jongshin Shin, Ilwon Seo, Jiyoung Kim, Seung-Hee Yang, Chiwon Kim, Jaehyun Park, Hyungoo Kim, Myoungbo Kwak, GhyBoong Hong:
A Low-Jitter Added SSCG with Seamless Phase Selection and Fast AFC for 3rd Generation Serial-ATA. 409-412 - Ricky Yuen, Marcus van Ierssel, Ali Sheikholeslami, William W. Walker, Hirotaka Tamura:
A 5Gb/s Transmitter with Reflection Cancellation for Backplane Transceivers. 413-416 - Amber Han-Yuan Tan, Gu-Yeon Wei:
Phase Mismatch Detection and Compensation for PLL/DLL Based Multi-Phase Clock Generator. 417-420 - Yasushi Yamagata, Hiroki Shirai, Hirotoshi Sugimura, S. Arai, Tomoko Wake, Ken Inoue, Takashi Sakoh, Masato Sakao, Takaho Tanigawa:
Device Technology for embedded DRAM utilizing stacked MIM(Metal-Insulator-Metal) Capacitor. 421-427 - Kazutami Arimoto, Fukashi Morishita, Isamu Hayashi, Tetsushi Tanizaki, Takashi Ipposhi, Katsumi Dosaka:
A Scalable ET2RAM (SETRAM) with Verify Control for SoC Platform Memory IP on SOI. 429-432 - Saakshi Gangwal, Saibal Mukhopadhyay, Kaushik Roy:
Optimization of Surface Orientation for High-Performance, Low-Power and Robust FinFET SRAM. 433-436 - Eishi Ibe, S. S. Chung, ShiJie Wen, Hironaru Yamaguchi, Yasuo Yahagi, Hideaki Kameyama, Shigehisa Yamamoto, Takashi Akioka:
Spreading Diversity in Multi-cell Neutron-Induced Upsets with Device Scaling. 437-444 - Kevin W. Gorman, Darren Anand, Gary Pomichter, William R. Corbin:
Low Cost Test of High Bandwidth Embedded Memories. 445-448 - Joe Walsh, G. Scott:
High-Temperature, High Reliability EEPROM Design For Automotive Applications. 449-452 - Igor Arsovski, Reid Wistort:
Self-referenced sense amplifier for across-chip-variation immune sensing in high-performance Content-Addressable Memories. 453-456 - Arijit Raychowdhury, Jeong I. Kim, Dimitrios Peroulis, Kaushik Roy:
Integrated MEMS Switches for Leakage Control of Battery Operated Systems. 457-460 - Jae Eun Jang, Seung Nam Cha, Youngjin Choi, Dae Joon Kang, Tim P. Butler, David G. Hasko, Jong Min Kim, Gehan A. J. Amaratunga:
CNT based mechanical devices for ULSI memory. 461-464 - Levent Yobas, Hongmiao Ji, Wing-Cheong Hui, Yu Chen, Tit Meng Lim, Chew-Kiat Heng, Dim-Lee Kwong:
Nucleic Acid Extraction, Amplification, and Detection on Si-based Microfluidic Platforms. 465-472 - Kenneth K. O, Kihong Kim, Brian A. Floyd, Jesal Mehta, Hyun Yoon, Chih-Ming Hung, Daniel F. Bravo, Timothy O. Dickson, Xiaoling Guo, Ran Li, Narasimhan Trichy, James Caserta, Wayne R. Bomstad II, Jason Branch, Dong-Jun Yang, Jose L. Bohorquez, Jie Chen, Eunyoung Seok, Joe E. Brewer, Li Gao, Aravind Sugavanam, Jau-Jr Lin, Y. Su, Changhua Cao, M.-H. Hwang, Yanping Ding, Zhenbiao Li, S.-H. Hwang, H. Wu, Swaminathan Sankaran, N. Zhang:
Silicon Integrated Circuits Incorporating Antennas. 473-480 - Ashutosh Verma, Behzad Razavi:
Frequency-Based Measurement of Mismatches Between Small Capacitors. 481-484 - Young-Jae Cho, Kyung-Hoon Lee, Hee-Cheol Choi, Seung-Hoon Lee, Kyoung-Ho Moon, Jae-Whui Kim:
A Calibration-Free 14b 70MS/s 3.3mm2 235mW 0.13um CMOS Pipeline ADC with High-Matching 3-D Symmetric Capacitors. 485-488 - Sunghyun Park, Yorgos Palaskas, Ashoke Ravi, Ralph E. Bishop, Michael P. Flynn:
A 3.5 GS/s 5-b Flash ADC in 90 nm CMOS. 489-492 - Shahriar Shahramian, Sorin P. Voinigescu, Anthony Chan Carusone:
A 30-GS/sec Track and Hold Amplifier in 0.13-μm CMOS Technology. 493-496 - Young-Jae Cho, Doo-Hwan Sa, Yong-Woo Kim, Kyung-Hoon Lee, Hee-Cheol Choi, Seung-Hoon Lee, Young-Deuk Jeon, Seung-Chul Lee, Jong-Kee Kwon:
A 10b 25MS/s 4.8mW 0.13um CMOS ADC for Digital Multimedia Broadcasting Applications. 497-500 - Takeshi Ueno, Tomohiko Ito, Daisuke Kurose, Takafumi Yamaji, Tetsuro Itakura:
A 1.2 V, 24 mW/ch, 10 bit, 80 MSample/s Pipelined A/D Converters. 501-504 - Shoji Kawahito:
Low-Power Design of Pipeline A/D Converters. 505-512 - Jian Li, Xiaoyang Zeng, Lei Xie, Jun Chen, Jianyun Zhang, Yawei Guo:
A 1.8-V 22-mW 10-bit 30-MS/s Subsampling Pipelined CMOS ADC. 513-516 - Robert Bogdan Staszewski, Khurram Muhammad, Dirk Leipold:
Digital Signal Processing for RF at 45-nm CMOS and Beyond. 517-522 - Dayu Yang, Weining Ni, Fa Foster Dai, Yin Shi, Richard C. Jaeger:
Delta-Sigma Modulation in Direct Digital Frequency Synthesis. 523-526 - Jonne Lindeberg, Olli Väänänen, Jussi Pirkkalaniemi, Marko Kosunen, Kari Halonen:
OFDM modulator with digital IF and on-chip D/A-converter. 527-530