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2020 – today
- 2024
[j102]Dongzhu Li, Zhijie Zhan, Rei Sumikawa, Mototsugu Hamada, Atsutake Kosuge, Tadahiro Kuroda:
A 0.13mJ/Prediction CIFAR-100 Fully Synthesizable Raster-Scan-Based Wired-Logic Processor in 16-nm FPGA. IEICE Trans. Electron. 107(6): 155-162 (2024)- [j101]Tadahiro Kuroda:
Slashing IC Power and Democratizing IC Access for the Digital Age. IPSJ Trans. Syst. LSI Des. Methodol. 17: 2-6 (2024) - [c132]Dongzhu Li, Tianqi Zhao
, Kenji Kobayashi, Atsutake Kosuge, Mototsugu Hamada, Tadahiro Kuroda:
Efficient FPGA Resource Utilization in Wired-Logic Processors Using Coarse and Fine Segmentation of LUTs for Non-Linear Functions. ISCAS 2024: 1-5 - 2023
- [j100]Kota Shiba, Atsutake Kosuge, Mototsugu Hamada, Tadahiro Kuroda:
Crosstalk Analysis and Countermeasures of High-Bandwidth 3D-Stacked Memory Using Multi-Hop Inductive Coupling Interface. IEICE Trans. Electron. 106(7): 391-394 (2023) - [j99]Kota Shiba, Mitsuji Okada, Atsutake Kosuge, Mototsugu Hamada, Tadahiro Kuroda:
A 7-nm FinFET 1.2-TB/s/mm2 3D-Stacked SRAM Module With 0.7-pJ/b Inductive Coupling Interface Using Over-SRAM Coil and Manchester-Encoded Synchronous Transceiver. IEEE J. Solid State Circuits 58(7): 2075-2086 (2023) - [j98]Atsutake Kosuge, Yao-Chung Hsu, Rei Sumikawa, Mototsugu Hamada, Tadahiro Kuroda, Tomoe Ishikawa:
A 10.7-µJ/Frame 88% Accuracy CIFAR-10 Single-Chip Neuromorphic Field-Programmable Gate Array Processor Featuring Various Nonlinear Functions of Dendrites in the Human Cerebrum. IEEE Micro 43(6): 19-27 (2023) - [j97]Kota Shiba, Mitsuji Okada, Atsutake Kosuge, Mototsugu Hamada, Tadahiro Kuroda:
Polyomino: A 3D-SRAM-Centric Accelerator for Randomly Pruned Matrix Multiplication With Simple Reordering Algorithm and Efficient Compression Format in 180-nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 70(9): 3440-3450 (2023) - [c131]Rei Sumikawa, Kota Shiba, Atsutake Kosuge, Mototsugu Hamada, Tadahiro Kuroda:
A 1.2nJ/Classification Fully Synthesized All-Digital Asynchronous Wired-Logic Processor Using Quantized Non-Linear Function Blocks in 0.18μm CMOS. ASP-DAC 2023: 180-181 - [c130]Yao-Chung Hsu, Atsutake Kosuge, Rei Sumikawa, Kota Shiba, Mototsugu Hamada, Tadahiro Kuroda:
A Fully Synthesized 13.7μJ/Prediction 88% Accuracy CIFAR-10 Single-Chip Data-Reusing Wired-Logic Processor Using Non-Linear Neural Network. ASP-DAC 2023: 182-183 - [c129]Eitaro Kobayashi, Atsutake Kosuge, Mototsugu Hamada, Tadahiro Kuroda:
An Occlusion-Resilient mmWave Imaging Radar-Based Object Recognition System Using Synthetic Training Data Generation Technique. IECON 2023: 1-6 - [c128]Dongzhu Li, Yao-Chung Hsu, Rei Sumikawa, Atsutake Kosuge, Mototsugu Hamada, Tadahiro Kuroda:
A 0.13mJ/Prediction CIFAR-100 Raster-Scan- Based Wired-Logic Processor Using Non-Linear Neural Network. ISCAS 2023: 1-5 - [c127]Ximing Wang, Atsutake Kosuge, Yasuhiro Hayashi, Kota Shiba, Mototsugu Hamada, Tadahiro Kuroda:
Analysis and Design of a 7 Gb/s Rotatable Non-contact Connector with Grid Array Package Application. NEWCAS 2023: 1-4 - [c126]Atsutake Kosuge, Rei Sumikawa, Yao-Chung Hsu, Kota Shiba, Mototsugu Hamada, Tadahiro Kuroda:
A 183.4nJ/inference 152.8μW Single-Chip Fully Synthesizable Wired-Logic DNN Processor for Always-On 35 Voice Commands Recognition Application. VLSI Technology and Circuits 2023: 1-2 - 2022
- [j96]Atsutake Kosuge, Mototsugu Hamada, Tadahiro Kuroda:
A 6.5Gb/s Shared Bus Using Electromagnetic Connectors for Downsizing and Lightening Satellite Processor System. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 105-A(3): 478-486 (2022) - [j95]Atsutake Kosuge, Mototsugu Hamada, Tadahiro Kuroda:
A 6-Gb/s Inductively-Powered Non-Contact Connector With Rotatable Transmission Line Coupler and Interface Bridge IC. IEEE J. Solid State Circuits 57(2): 535-545 (2022) - [j94]Atsutake Kosuge, Yao-Chung Hsu, Mototsugu Hamada, Tadahiro Kuroda:
A 0.61-μJ/Frame Pipelined Wired-logic DNN Processor in 16-nm FPGA Using Convolutional Non-Linear Neural Network. IEEE Open J. Circuits Syst. 3: 4-14 (2022) - [j93]Atsutake Kosuge, Tadahiro Kuroda:
Proximity Wireless Communication Technologies: An Overview and Design Guidelines. IEEE Trans. Circuits Syst. I Regul. Pap. 69(11): 4317-4330 (2022) - [j92]Atsutake Kosuge, Satoshi Suehiro, Mototsugu Hamada, Tadahiro Kuroda:
mmWave-YOLO: A mmWave Imaging Radar-Based Real-Time Multiclass Object Recognition System for ADAS Applications. IEEE Trans. Instrum. Meas. 71: 1-10 (2022) - [c125]Reiji Miura, Saito Shibata, Masahiro Usui, Atsutake Kosuge, Mototsugu Hamada, Tadahiro Kuroda:
A 5.2GHz RFID Chip Contactlessly Mountable on FPC at any 90-Degree Rotation and Face Orientation. ASP-DAC 2022: 5-6 - [c124]Yao-Chung Hsu, Atsutake Kosuge, Rei Sumikawa, Kota Shiba, Mototsugu Hamada, Tadahiro Kuroda:
A 13.7μJ/prediction 88% Accuracy CIFAR-10 Single-Chip Wired-logic Processor in 16-nm FPGA using Non-Linear Neural Network. HCS 2022: 1-14 - [c123]Kota Shiba, Mitsuji Okada, Atsutake Kosuge, Mototsugu Hamada, Tadahiro Kuroda:
A 7-nm FinFET 1.2-TB/s/mm2 3D-Stacked SRAM with an Inductive Coupling Interface Using Over-SRAM Coils and Manchester-Encoded Synchronous Transceivers. HCS 2022: 1-14 - [c122]Saito Shibata, Yoshiki Sawabe, Kota Shiba, Atsutake Kosuge, Mototsugu Hamada, Tadahiro Kuroda:
A Low-power RFID with 100kbps Data Rate Employing High-speed Power Clock Generator for Complementary Pass-transistor Adiabatic Logic. ICECS 2022 2022: 1-4 - [c121]Ximing Wang, Atsutake Kosuge, Yasuhiro Hayashi, Mototsugu Hamada, Tadahiro Kuroda:
A 7 Gb/s Micro Rotatable Transmission Line Coupler with Deep Proximity Coupling Mode and Ground Shielding Vias. ICECS 2022 2022: 1-4 - [c120]Kota Shiba, Mitsuji Okada, Atsutake Kosuge, Mototsugu Hamada, Tadahiro Kuroda:
Polyomino: A 3D-SRAM-Centric Architecture for Randomly Pruned Matrix Multiplication with Simple Rearrangement Algorithm and x0.37 Compression Format. NEWCAS 2022: 99-103 - [c119]Lixing Yu, Atsutake Kosuge, Mototsugu Hamada, Tadahiro Kuroda:
An Anomaly Detection System for Transparent Objects Using Polarized-Image Fusion Technique. SAS 2022: 1-6 - 2021
- [j91]Atsutake Kosuge, Mototsugu Hamada, Tadahiro Kuroda:
A 16 nJ/Classification FPGA-Based Wired-Logic DNN Accelerator Using Fixed-Weight Non-Linear Neural Net. IEEE J. Emerg. Sel. Topics Circuits Syst. 11(4): 751-761 (2021) - [j90]Kota Shiba, Tatsuo Omori, Kodai Ueyoshi, Shinya Takamaeda-Yamazaki, Masato Motomura, Mototsugu Hamada, Tadahiro Kuroda:
A 96-MB 3D-Stacked SRAM Using Inductive Coupling With 0.4-V Transmitter, Termination Scheme and 12: 1 SerDes in 40-nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 68(2): 692-703 (2021) - [c118]Kota Shiba, Tatsuo Omori, Mototsugu Hamada, Tadahiro Kuroda:
A 3D-Stacked SRAM Using Inductive Coupling Technology for AI Inference Accelerator in 40-nm CMOS. ASP-DAC 2021: 97-98 - [c117]Tatsuo Omori, Kota Shiba, Mototsugu Hamada, Tadahiro Kuroda:
Sub-10-μm Coil Design for Multi-Hop Inductive Coupling Interface. ASP-DAC 2021: 99-100 - [c116]Saito Shibata, Reiji Miura, Yoshiki Sawabe, Kota Shiba, Atsutake Kosuge, Mototsugu Hamada, Tadahiro Kuroda:
A 5-GHz 0.15-mm2 Collision Avoidable RFID Employing Complementary Pass-transistor Adiabatic Logic with an Inductively Connected External Antenna. A-SSCC 2021: 1-3 - [c115]Shohei Morinaga, Tomoe Ishikawa, Masato Yasui, Mototsugu Hamada, Tadahiro Kuroda:
CA2 area detection from hippocampal microscope images using deep learning. MWSCAS 2021: 603-606 - 2020
- [c114]Kohei Ando, Kazuhisa Akatsuka, Chaoran Cheng, Tomoya Arakawa, Kota Shiba, Mototsugu Hamada, Tadahiro Kuroda:
A 50 Mbps/pin 12-input/output 40 nsec Latency Wireless Connector Using a Transmission Line Coupler with Compact SERDES IC in 180 nm CMOS. ICECS 2020: 1-4 - [c113]Kota Shiba, Tatsuo Omori, Kodai Ueyoshi, Kota Ando, Kazutoshi Hirose, Shinya Takamaeda-Yamazaki, Masato Motomura, Mototsugu Hamada, Tadahiro Kuroda:
A 3D-Stacked SRAM using Inductive Coupling with Low-Voltage Transmitter and 12: 1 SerDes. ISCAS 2020: 1-5
2010 – 2019
- 2019
- [j89]Mototsugu Hamada, Tadahiro Kuroda:
Transmission Line Coupler: High-Speed Interface for Non-Contact Connecter. IEICE Trans. Electron. 102-C(7): 501-508 (2019) - [j88]Kodai Ueyoshi, Kota Ando, Kazutoshi Hirose, Shinya Takamaeda-Yamazaki, Mototsugu Hamada, Tadahiro Kuroda, Masato Motomura:
QUEST: Multi-Purpose Log-Quantized DNN Inference Engine Stacked on 96-MB 3-D SRAM Using Inductive Coupling Technology in 40-nm CMOS. IEEE J. Solid State Circuits 54(1): 186-196 (2019) - [c112]Tomoya Arakawa, Joshin Sone, Mitsuji Okada, Mototsugu Hamada, Tadahiro Kuroda:
Live Demonstration: A Non-Contact Transmission Line Connector for USB3.1 HD-Video Streaming. ISCAS 2019: 1 - [c111]Takahisa Tanaka, K. Tabuchi, Kohei Tatehora, Yohsuke Shiiki, S. Nakagawa, Tsunaki Takahashi, R. Shimizu, Hiroki Ishikuro, Tadahiro Kuroda, T. Yanagida, Ken Uchida:
Low-Power and ppm-Level Detection of Gas Molecules by Integrated Metal Nanosheets. VLSI Circuits 2019: 158- - 2018
- [j87]Shusuke Yanagawa, Ryota Shimizu, Mototsugu Hamada, Toru Shimizu, Tadahiro Kuroda:
Optimization of Resonant Capacitance in Wireless Power Transfer System with 3-D Stacked Two Receivers. IEICE Trans. Electron. 101-C(7): 488-492 (2018) - [j86]Akio Nomura, Yusuke Matsushita, Junichiro Kadomoto, Hiroki Matsutani, Tadahiro Kuroda, Hideharu Amano:
Escalator Network for a 3D Chip Stack with Inductive Coupling ThruChip Interface. Int. J. Netw. Comput. 8(1): 124-139 (2018) - [j85]Kota Ando, Kodai Ueyoshi, Kentaro Orimo, Haruyoshi Yonekawa, Shimpei Sato, Hiroki Nakahara, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Tetsuya Asai, Tadahiro Kuroda, Masato Motomura:
BRein Memory: A Single-Chip Binary/Ternary Reconfigurable in-Memory Deep Neural Network Accelerator Achieving 1.4 TOPS at 0.6 W. IEEE J. Solid State Circuits 53(4): 983-994 (2018) - [c110]Ryota Shimizu, Kosuke Asako, Hiroki Ojima, Shohei Morinaga, Mototsugu Hamada, Tadahiro Kuroda:
Balanced Mini-Batch Training for Imbalanced Image Data Classification with Neural Network. AI4I 2018: 27-30 - [c109]Shusuke Yanagawa, Ryota Shimizu, Mototsugu Hamada, Toru Shimizu, Tadahiro Kuroda:
Design Methodology in Wireless Power Transfer System for 3-D Stacked Multiple Receivers. ISCAS 2018: 1-4 - [c108]Kodai Ueyoshi, Kota Ando, Kazutoshi Hirose, Shinya Takamaeda-Yamazaki, Junichiro Kadomoto, Tomoki Miyata, Mototsugu Hamada, Tadahiro Kuroda, Masato Motomura:
QUEST: A 7.49TOPS multi-purpose log-quantized DNN inference engine stacked on 96MB 3D SRAM using inductive-coupling technology in 40nm CMOS. ISSCC 2018: 216-218 - [c107]Tsuyoshi Maruyama, Mototsugu Hamada, Tadahiro Kuroda:
Comparative Performance Analysis of Dual-Rail Domino Logic and CMOS Logic Under NearThreshold Operation. MWSCAS 2018: 25-28 - [c106]Shusuke Yanagawa, Ryota Shimizu, Mototsugu Hamada, Tadahiro Kuroda:
Wireless Power Transfer System for 3-D stacked Multiple Receivers Switching between Single and Dual Frequency Modes. MWSCAS 2018: 1046-1049 - [c105]Yuta Toeda, Takumi Fujimaki, Mototsugu Hamada, Tadahiro Kuroda:
Fully Integrated OOK-Powered Pad-Less Deep Sub-Wavelength-Sized 5-GHz RFID with On-Chip Antenna Using Adiabatic Logic in 0.18μM CMOS. VLSI Circuits 2018: 27-28 - 2017
- [c104]Masayuki Ikebe, Tetsuya Asai, Masafumi Mori, Toshiyuki Itou, Daisuke Uchida, Yasuhiro Take, Tadahiro Kuroda, Masato Motomura:
An image sensor/processor 3D stacked module featuring ThruChip interfaces. ASP-DAC 2017: 7-8 - [c103]Akio Nomura, Junichiro Kadomoto, Tadahiro Kuroda, Hideharu Amano:
A Practical Collision Avoidance Method for an Inter-Chip Bus with Wireless Inductive through Chip Interface. CANDAR 2017: 126-131 - [c102]Shusuke Yanagawa, Ryota Shimizu, Mototsugu Hamada, Toru Shimizu, Tadahiro Kuroda:
Wireless power transfer to stacked modules for IoT sensor nodes. ISOCC 2017: 59-60 - [c101]Ryota Shimizu, Shusuke Yanagawa, Toru Shimizu, Mototsugu Hamada, Tadahiro Kuroda:
Convolutional neural network for industrial egg classification. ISOCC 2017: 67-68 - [c100]Junichiro Kadomoto, Hideharu Amano, Tadahiro Kuroda:
An inductive-coupling link for 3-D Network-on-Chips. ISOCC 2017: 150-151 - [c99]Hideharu Amano, Tadahiro Kuroda, Hiroshi Nakamura, Kimiyoshi Usami, Masaaki Kondo, Hiroki Matsutani, Mitaro Namiki:
Building block multi-chip systems using inductive coupling through chip interface. ISOCC 2017: 152-154 - 2016
- [j84]Junichiro Kadomoto, So Hasegawa, Yusuke Kiuchi, Atsutake Kosuge, Tadahiro Kuroda:
Analysis and Evaluation of Electromagnetic Interference between ThruChip Interface and LC-VCO. IEICE Trans. Electron. 99-C(6): 659-662 (2016) - [j83]Atsutake Kosuge, Junki Hashiba, Toru Kawajiri, So Hasegawa, Tsunaaki Shidei, Hiroki Ishikuro, Tadahiro Kuroda, Ken Takeuchi:
An Inductively Powered Wireless Solid-State Drive System With Merged Error Correction of High-Speed Wireless Data Links and NAND Flash Memories. IEEE J. Solid State Circuits 51(4): 1041-1050 (2016) - [j82]Atsutake Kosuge, Junichiro Kadomoto, Tadahiro Kuroda:
A 6 Gb/s 6 pJ/b 5 mm-Distance Non-Contact Interface for Modular Smartphones Using Two-Fold Transmission Line Coupler and High EMC Tolerant Pulse Transceiver. IEEE J. Solid State Circuits 51(6): 1446-1456 (2016) - [j81]Atsutake Kosuge, Akira Okada, Masao Taguchi, Hiroki Ishikuro, Tadahiro Kuroda:
A 280 Mb/s In-Vehicle LAN System Using Electromagnetic Clip Connector and High-EMC Transceiver. IEEE Trans. Circuits Syst. I Regul. Pap. 63-I(2): 265-275 (2016) - [j80]Takahiro Kagami, Hiroki Matsutani, Michihiro Koibuchi, Yasuhiro Take, Tadahiro Kuroda, Hideharu Amano:
Efficient 3-D Bus Architectures for Inductive-Coupling ThruChip Interfaces. IEEE Trans. Very Large Scale Integr. Syst. 24(2): 493-506 (2016) - [c98]Li-Chung Hsu, Junichiro Kadomoto, So Hasegawa, Atsutake Kosuge, Yasuhiro Take, Tadahiro Kuroda:
Analytical thruchip inductive coupling channel design optimization. ASP-DAC 2016: 731-736 - [c97]Junichiro Kadomoto, Tomoki Miyata, Hideharu Amano, Tadahiro Kuroda:
An inductive-coupling bus with collision detection scheme using magnetic field variation for 3-D network-on-chips. A-SSCC 2016: 41-44 - [c96]Tetsuya Asai, Masafumi Mori, Toshiyuki Itou, Yasuhiro Take, Masayuki Ikebe, Tadahiro Kuroda, Masato Motomura:
Motion-vector estimation and cognitive classification on an image sensor/processor 3D stacked system featuring ThruChip interfaces. ESSCIRC 2016: 105-108 - [c95]So Hasegawa, Junichiro Kadomoto, Atsutake Kosuge, Tadahiro Kuroda:
A 1 Tb/s/mm2 inductive-coupling side-by-side chip link. ESSCIRC 2016: 469-472 - [c94]Akio Nomura, Hiroki Matsutani, Tadahiro Kuroda, Junichiro Kadomoto, Yusuke Matsushita, Hideharu Amano:
Vertical Packet Switching Elevator Network Using Inductive Coupling ThruChip Interface. CANDAR 2016: 195-201 - [c93]Ryota Shimizu, Shusuke Yanagawa, Yasutaka Monde, Hiroki Yamagishi, Mototsugu Hamada, Toru Shimizu, Tadahiro Kuroda:
Deep learning application trial to lung cancer diagnosis for medical sensor systems. ISOCC 2016: 191-192 - [c92]Ahmad Muzaffar bin Baharudin, Mika Saari, Pekka Sillberg, Petri Rantanen, Jari Soini, Tadahiro Kuroda:
Low-energy algorithm for self-controlled Wireless Sensor Nodes. WINCOM 2016: 42-46 - 2015
- [j79]Li-Chung Hsu, Masato Motomura, Yasuhiro Take, Tadahiro Kuroda:
Through Chip Interface Based Three-Dimensional FPGA Architecture Exploration. IEICE Trans. Electron. 98-C(4): 288-297 (2015) - [j78]Yasuhiro Take, Tadahiro Kuroda:
Relay Transmission Thruchip Interface with Low-Skew 3D Clock Distribution Network. IEICE Trans. Electron. 98-C(4): 322-332 (2015) - [j77]Takahide Terada, Haruki Fukuda, Tadahiro Kuroda:
Transponder Array System with Universal On-Sheet Reference Scheme for Wireless Mobile Sensor Networks without Battery or Oscillator. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 98-A(4): 932-941 (2015) - [j76]Li-Chung Hsu, Junichiro Kadomoto, So Hasegawa, Atsutake Kosuge, Yasuhiro Take, Tadahiro Kuroda:
A Study of Physical Design Guidelines in ThruChip Inductive Coupling Channel. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 98-A(12): 2584-2591 (2015) - [j75]Kamal El-Sankary, Tetsuya Asai, Masato Motomura, Tadahiro Kuroda:
Crosstalk Rejection in 3-D-Stacked Interchip Communication With Blind Source Separation. IEEE Trans. Circuits Syst. II Express Briefs 62-II(8): 726-730 (2015) - [j74]Atsutake Kosuge, Shu Ishizuka, Masao Taguchi, Hiroki Ishikuro, Tadahiro Kuroda:
Analysis and Design of an 8.5-Gb/s/Link Multi-Drop Bus Using Energy-Equipartitioned Transmission Line Couplers. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(8): 2122-2131 (2015) - [j73]Kentaro Yoshioka, Akira Shikata, Ryota Sekimoto, Tadahiro Kuroda, Hiroki Ishikuro:
An 8 bit 0.3-0.8 V 0.2-40 MS/s 2-bit/Step SAR ADC With Successively Activated Threshold Configuring Comparators in 40 nm CMOS. IEEE Trans. Very Large Scale Integr. Syst. 23(2): 356-368 (2015) - [c91]Akira Okada, Abdul Raziz Junaidi, Yasuhiro Take, Atsutake Kosuge, Tadahiro Kuroda:
Circuit and package design for 44GB/s inductive-coupling DRAM/SoC interface. ASP-DAC 2015: 44-45 - [c90]Li-Chung Hsu, Yasuhiro Take, Atsutake Kosuge, So Hasegawa, Junichiro Kadamoto, Tadahiro Kuroda:
Design and analysis for ThruChip design for manufacturing (DFM). ASP-DAC 2015: 46-47 - [c89]Atsutake Kosuge, Shu Ishizuka, Marni Abe, Satoshi Ichikawa, Tadahiro Kuroda:
24.4 A 6.5Gb/s Shared bus using electromagnetic connectors for downsizing and lightening satellite processor system by 60%. ISSCC 2015: 1-3 - [c88]Atsutake Kosuge, Shu Ishizuka, Junichiro Kadomoto, Tadahiro Kuroda:
10.1 A 6Gb/s 6pJ/b 5mm-distance non-contact interface for modular smartphones using two-fold transmission-line coupler and EMC-qualified pulse transceiver. ISSCC 2015: 1-3 - [c87]Masayuki Ikebe, Daisuke Uchida, Yasuhiro Take, Makito Someya, Satoshi Chikuda, Kento Matsuyama, Tetsuya Asai, Tadahiro Kuroda, Masato Motomura:
Image sensor/digital logic 3D stacked module featuring inductive coupling channels for high speed/low-noise image transfer. VLSIC 2015: 82- - [c86]Atsutake Kosuge, Junki Hashiba, Toru Kawajiri, So Hasegawa, Tsunaaki Shidei, Hiroki Ishikuro, Tadahiro Kuroda, Ken Takeuchi:
Inductively-powered wireless solid-state drive (SSD) system with merged error correction of high-speed non-contact data links and NAND flash memory. VLSIC 2015: 128- - 2014
- [j72]Lechang Liu, Keisuke Ishikawa, Tadahiro Kuroda:
Parametric Resonance Based Frequency Multiplier for Sub-Gigahertz Radio Receiver with 0.3V Supply Voltage. IEICE Trans. Electron. 97-C(6): 505-511 (2014) - [j71]Yi Zhan, Tadahiro Kuroda:
Wearable sensor-based human activity recognition from environmental background sounds. J. Ambient Intell. Humaniz. Comput. 5(1): 77-89 (2014) - [j70]Timothy C. Fischer, Byeong-Gyu Nam, Leland Chang, Tadahiro Kuroda, Michiel A. P. Pertijs:
Highlights of the ISSCC 2013 Processors and High Performance Digital Sessions. IEEE J. Solid State Circuits 49(1): 4-8 (2014) - [j69]Atsutake Kosuge, Wataru Mizuhara, Tsunaaki Shidei, Tsutomu Takeya, Noriyuki Miura, Masao Taguchi, Hiroki Ishikuro, Tadahiro Kuroda:
A 0.15-mm-Thick Noncontact Connector for MIPI Using a Vertical Directional Coupler. IEEE J. Solid State Circuits 49(1): 223-231 (2014) - [j68]Yasuhiro Take, Hiroki Matsutani, Daisuke Sasaki, Michihiro Koibuchi, Tadahiro Kuroda, Hideharu Amano:
3D NoC with Inductive-Coupling Links for Building-Block SiPs. IEEE Trans. Computers 63(3): 748-763 (2014) - [c85]Kentaro Yoshioka, Akira Shikata, Ryota Sekimoto, Tadahiro Kuroda, Hiroki Ishikuro:
An 8b extremely area efficient threshold configuring SAR ADC with source voltage shifting technique. ASP-DAC 2014: 31-32 - [c84]Hiroki Matsutani, Michihiro Koibuchi, Ikki Fujiwara, Takahiro Kagami, Yasuhiro Take, Tadahiro Kuroda, Paul Bogdan, Radu Marculescu, Hideharu Amano:
Low-latency wireless 3D NoCs via randomized shortcut chips. DATE 2014: 1-6 - [c83]Atsutake Kosuge, Shu Ishizuka, Lechang Liu, Akira Okada, Masao Taguchi, Hiroki Ishikuro, Tadahiro Kuroda:
30.6 An electromagnetic clip connector for in-vehicle LAN to reduce wire harness weight by 30%. ISSCC 2014: 496-497 - [c82]Yusuke Oike, Makoto Ikeda, Albert Theuwissen, Johannes Solhusvik, Jonathan Chang, Tadahiro Kuroda:
F2: 3D stacking technologies for image sensors and memories. ISSCC 2014: 512-513 - [c81]Abdul Raziz Junaidi, Yasuhiro Take, Tadahiro Kuroda:
A 352Gb/s inductive-coupling DRAM/SoC interface using overlapping coils with phase division multiplexing and ultra-thin fan-out wafer level package. VLSIC 2014: 1-2 - 2013
- [j67]Akira Shikata, Ryota Sekimoto, Kentaro Yoshioka, Tadahiro Kuroda, Hiroki Ishikuro:
A 4-10 bit, 0.4-1 V Power Supply, Power Scalable Asynchronous SAR-ADC in 40 nm-CMOS with Wide Supply Voltage Range SAR Controller. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 96-A(2): 443-452 (2013) - [j66]Tsutomu Takeya, Tadahiro Kuroda:
Symbol-Rate Clock Recovery for Integrating DFE Receivers. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 96-A(3): 705-712 (2013) - [j65]Tsutomu Takeya, Tadahiro Kuroda:
Transmission Line Coupler Design and Mixer-Based Receiver for Dicode Partial Response Communications. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 96-A(5): 940-946 (2013) - [j64]Ryota Sekimoto, Akira Shikata, Kentaro Yoshioka, Tadahiro Kuroda, Hiroki Ishikuro:
An Adaptive DAC Settling Waiting Time Optimized Ultra Low Voltage Asynchronous SAR ADC in 40 nm CMOS. IEICE Trans. Electron. 96-C(6): 820-827 (2013) - [j63]Hao Zhang, Hiroki Matsutani, Yasuhiro Take, Tadahiro Kuroda, Hideharu Amano:
Vertical Link On/Off Regulations for Inductive-Coupling Based Wireless 3-D NoCs. IEICE Trans. Inf. Syst. 96-D(12): 2753-2764 (2013) - [j62]Tsutomu Takeya, Lan Nan, Shinya Nakano, Noriyuki Miura, Hiroki Ishikuro, Tadahiro Kuroda:
A 12-Gb/s Non-Contact Interface With Coupled Transmission Lines. IEEE J. Solid State Circuits 48(3): 790-800 (2013) - [j61]Ryota Sekimoto, Akira Shikata, Kentaro Yoshioka, Tadahiro Kuroda, Hiroki Ishikuro:
A 0.5-V 5.2-fJ/Conversion-Step Full Asynchronous SAR ADC With Leakage Power Reduction Down to 650 pW by Boosted Self-Power Gating in 40-nm CMOS. IEEE J. Solid State Circuits 48(11): 2628-2636 (2013) - [j60]Noriyuki Miura, Yusuke Koizumi, Yasuhiro Take, Hiroki Matsutani, Tadahiro Kuroda, Hideharu Amano, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo, Hiroshi Nakamura:
A Scalable 3D Heterogeneous Multicore with an Inductive ThruChip Interface. IEEE Micro 33(6): 6-15 (2013) - [c80]Hiroki Matsutani, Paul Bogdan, Radu Marculescu, Yasuhiro Take, Daisuke Sasaki, Hao Zhang, Michihiro Koibuchi, Tadahiro Kuroda, Hideharu Amano:
A case for wireless 3D NoCs for CMPs. ASP-DAC 2013: 23-28 - [c79]Atsutake Kosuge, Wataru Mizuhara, Noriyuki Miura, Masao Taguchi, Hiroki Ishikuro, Tadahiro Kuroda:
A 12.5Gb/s/link non-contact multi drop bus system with impedance-matched Transmission Line Couplers and Dicode partial-response channel transceivers. ASP-DAC 2013: 91-92 - [c78]Kentaro Yoshioka, Akira Shikata, Ryota Sekimoto, Tadahiro Kuroda, Hiroki Ishikuro:
A 0.35-0.8V 8b 0.5-35MS/s 2bit/step extremely-low power SAR ADC. ASP-DAC 2013: 111-112 - [c77]Noriyuki Miura, Yusuke Koizumi, Eiichi Sasaki, Yasuhiro Take, Hiroki Matsutani, Tadahiro Kuroda, Hideharu Amano, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo, Hiroshi Nakamura:
A scalable 3D heterogeneous multi-core processor with inductive-coupling thruchip interface. COOL Chips 2013: 1-3 - [c76]Yusuke Koizumi, Noriyuki Miura, Yasuhiro Take, Hiroki Matsutani, Tadahiro Kuroda, Hideharu Amano, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo, Hiroshi Nakamura:
Demonstration of a heterogeneous multi-core processor with 3-D inductive coupling links. FPL 2013: 1 - [c75]Noriyuki Miura, Yusuke Koizumi, Eiichi Sasaki, Yasuhiro Take, Hiroki Matsutani, Tadahiro Kuroda, Hideharu Amano, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo, Hiroshi Nakamura:
A scalable 3D heterogeneous multi-core processor with inductive-coupling thruchip interface. Hot Chips Symposium 2013: 1 - [c74]Katsuki Ohata, Yukitoshi Sanada, Tetsuro Ogaki, Kento Matsuyama, Takanori Ohira, Satoshi Chikuda, Masaki Igarashi, Masayuki Ikebe, Tetsuya Asai, Masato Motomura, Tadahiro Kuroda:
Hardware-oriented stereo vision algorithm based on 1-D guided filtering and its FPGA implementation. ICECS 2013: 169-172 - [c73]Yuki Ono, Abdul Raziz Junaidi, Tadahiro Kuroda:
Adaptive window search using semantic texton forests for real-time object detection. ICIP 2013: 3293-3296 - [c72]Yuki Urano, Won-Joo Yun, Tadahiro Kuroda, Hiroki Ishikuro:
A 1.26mW/Gbps 8 locking cycles versatile all-digital CDR with TDC combined DLL. ISCAS 2013: 1576-1579 - [c71]