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2020 – today
- 2022
[j3]Timothy M. Hollis
, Ronny Schneider, Martin Brox, Thomas Hein, Wolfgang Spirkl, Martin Bach, Mani Balakrishnan, Stefan Dietrich, Fabien Funfrock, Milena Ivanov, Natalija Jovanovic, Maksim Kuzmenka, Daniel Lauber, Juan Ocon Garrido, David Ovard, Karl Pfefferl, Sven Piatkowski, Gabriele Piscopo, Manfred Plan, Jens Polney, Jan Pottgiesser, Stephan Rau, Filippo Vitale, Marc Walter, Marcos Alvarez Gonzalez, Cristian Chetreanu, Andrea Sorrentino, Jörg Weller, Peter Mayer, Michael Richter, Casto Salobrena Garcia, Andreas Schneider, Shih Nern Wong:
An 8-Gb GDDR6X DRAM Achieving 22 Gb/s/pin With Single-Ended PAM-4 Signaling. IEEE J. Solid State Circuits 57(1): 224-235 (2022)- 2021
- [c8]Timothy M. Hollis, Ronny Schneider, Martin Brox, Thomas Hein, Wolfgang Spirkl, Martin Bach, Mani Balakrishnan, Stefan Dietrich, Fabien Funfrock, Milena Ivanov, Natalija Jovanovic, Maksim Kuzmenka, Daniel Lauber, Juan Ocon Garrido, David Ovard, Karl Pfefferl, Sven Piatkowski, Gabriele Piscopo, Manfred Plan, Jens Polney, Jan Pottgiesser, Stephan Rau, Filippo Vitale, Marc Walter, Marcos Alvarez Gonzalez, Martin Broschwitz, Cristian Chetreanu, Andrea Sorrentino, Jörg Weller, Peter Mayer, Michael Richter, Casto Salobrena Garcia, Andreas Schneider, Shih Nern Wong:
25.3 An 8Gb GDDR6X DRAM Achieving 22Gb/s/pin with Single-Ended PAM4 Signaling. ISSCC 2021: 348-350
2010 – 2019
- 2018
- [j2]Martin Brox, Mani Balakrishnan, Martin Broschwitz, Cristian Chetreanu, Stefan Dietrich, Fabien Funfrock, Marcos Alvarez Gonzalez, Thomas Hein, Eugen Huber, Daniel Lauber, Milena Ivanov, Maksim Kuzmenka, Chris Mohr, Juan Ocon Garrido, Swetha Padaraju, Sven Piatkowski, Jan Pottgiesser, Peter Pfefferl, Manfred Plan, Jens Polney, Stephan Rau, Michael Richter, Ronny Schneider, Ralf Oliver Seitter, Wolfgang Spirkl, Marc Walter, Jörg Weller, Filippo Vitale:
An 8-Gb 12-Gb/s/pin GDDR5X DRAM for Cost-Effective High-Performance Applications. IEEE J. Solid State Circuits 53(1): 134-143 (2018) - 2017
- [c7]Martin Brox, Mani Balakrishnan, Martin Broschwitz, Cristian Chetreanu, Stefan Dietrich, Fabien Funfrock, Marcos Alvarez Gonzalez, Thomas Hein, Eugen Huber, Daniel Lauber, Milena Ivanov, Maksim Kuzmenka, Chris Mohr, Francisco Emiliano Munoz, Juan Ocon Garrido, Swetha Padaraju, Sven Piatkowski, Jan Pottgiesser, Peter Pfefferl, Manfred Plan, Jens Polney, Stefan Rau, Michael Richter, Ronny Schneider, Ralf Oliver Seitter, Wolfgang Spirkl, Marc Walter, Jörg Weller, Filippo Vitale:
23.1 An 8Gb 12Gb/s/pin GDDR5X DRAM for cost-effective high-performance applications. ISSCC 2017: 388-389 - [c6]Martin Brox, Jonathan Chang, Howard C. Luong, Paul Liang, Riccardo Mariani:
EE5: When will we stop driving our cars? ISSCC 2017: 524 - 2016
- [c5]Chulwoo Kim, Martin Brox:
Session 18 overview: High-bandwidth DRAM. ISSCC 2016: 312-313 - [c4]Ichiro Fujimori, Martin Brox, Elad Alon, Pavan Kumar Hanumolu, Gerrit den Besten, Hideyuki Nosaka:
F4: Emerging short-reach and high-density interconnect solutions for internet of everything. ISSCC 2016: 502-505 - 2010
- [j1]Rex Kho, David Boursin, Martin Brox, Peter Gregorius, Heinz Hoenigschmid, Bianka Kho, Sabine Kieser, Daniel Kehrer, Maksim Kuzmenka, Udo Moeller, Pavel Veselinov Petkov, Manfred Plan, Michael Richter, Ian Russell, Kai Schiller, Ronny Schneider, Kartik Swaminathan, Bradley Weber, Julien Weber, Ingo Bormann, Fabien Funfrock, Mario Gjukic, Wolfgang Spirkl, Holger Steffens, Jörg Weller, Thomas Hein:
A 75 nm 7 Gb/s/pin 1 Gb GDDR5 Graphics Memory Device With Bandwidth Improvement Techniques. IEEE J. Solid State Circuits 45(1): 120-133 (2010)
2000 – 2009
- 2009
- [c3]Rex Kho, David Boursin, Martin Brox, Peter Gregorius, Heinz Hoenigschmid, Bianka Kho, Sabine Kieser, Daniel Kehrer, Maksim Kuzmenka, Udo Moeller, Pavel Veselinov Petkov, Manfred Plan, Michael Richter, Ian Russell, Kai Schiller, Ronny Schneider, Kartik Swaminathan, Bradley Weber, Julien Weber, Ingo Bormann, Fabien Funfrock, Mario Gjukic, Wolfgang Spirkl, Holger Steffens, Jörg Weller, Thomas Hein:
75nm 7Gb/s/pin 1Gb GDDR5 graphics memory device with bandwidth-improvement techniques. ISSCC 2009: 134-135 - 2007
- [c2]Martin Brox, Kazuhiko Kajigaya:
DRAM and eRAM. ISSCC 2007: 484-485 - 2006
- [c1]Martin Brox, H. Fibranz, Maksim Kuzmenka, F. Lu, S. Mann, M. Markert, U. Möller, Manfred Plan, Kai Schiller, P. Schmölz, P. Schrögmeier, A. Täuber, Bradley Weber, Peter Mayer, Wolfgang Spirkl, Holger Steffens, Jörg Weller:
A 2Gb/s/pin 512Mb Graphics DRAM with NoiseReduction Techniques. ISSCC 2006: 537-546
Coauthor Index
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