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ORCIDJyothi Velamala
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Journal Articles
- 2014
[j3]Yu Cao
, Jyothi Velamala, Ketul Sutaria, Mike Shuo-Wei Chen, Jonathan Ahlbin, Ivan Sanchez Esqueda, Michael Bajura, Michael Fritze:
Cross-Layer Modeling and Simulation of Circuit Reliability. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(1): 8-23 (2014)- 2012
- [j2]Jin Sun, Rui Zheng, Jyothi Velamala, Yu Cao, Roman L. Lysecky, Karthik Shankar, Janet Meiling Wang Roveda:
A self-tuning design methodology for power-efficient multi-core systems. ACM Trans. Design Autom. Electr. Syst. 18(1): 4:1-4:24 (2012) - 2011
- [j1]Evelyn Mintarno, Joëlle Skaf, Rui Zheng, Jyothi Velamala, Yu Cao, Stephen P. Boyd, Robert W. Dutton, Subhasish Mitra:
Self-Tuning for Maximized Lifetime Energy-Efficiency in the Presence of Circuit Aging. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(5): 760-773 (2011)
Conference and Workshop Papers
- 2023
- [c13]Rachael J. Parker, Jyothi Bhaskarr Velamala, Kuan-Yueh James Shen, David Johnston, Yao-Feng Chang, Stephen M. Ramey, Siang-jhih Sean Wu, Padma Penmatsa:
A Physical Unclonable Function Leveraging Hot Carrier Injection Aging. IRPS 2023: 1-5 - 2022
- [c12]Jyothi Bhaskarr Velamala, Siang-jhih Sean Wu, Padma Penmatsa, Kuan-Yueh James Shen, David Johnston, Rachael J. Parker:
PVT Tolerant Zero Bit-Error-Rate Physical Unclonable Function Exploiting Hot Carrier Injection Aging in 7nm FinFET Technology. CICC 2022: 1-2 - 2015
- [c11]Norbert Seifert, Shah M. Jahinuzzaman, Jyothi Velamala, Nikunj Patel:
Susceptibility of planar and 3D tri-gate technologies to muon-induced single event upsets. IRPS 2015: 2 - 2012
- [c10]Jyothi Velamala, Ketul Sutaria, Hirofumi Shimizu, Hiromitsu Awano, Takashi Sato, Yu Cao:
Statistical aging under dynamic voltage scaling: A logarithmic model approach. CICC 2012: 1-4 - [c9]Jyothi Bhaskarr Velamala, Ketul Sutaria, Takashi Sato, Yu Cao:
Physics matters: statistical aging prediction under trapping/detrapping. DAC 2012: 139-144 - 2011
- [c8]Jyothi Velamala, Robert LiVolsi, Myra Torres, Yu Cao:
Design sensitivity of single event transients in scaled logic circuits. DAC 2011: 694-699 - [c7]Jyothi Bhaskarr Velamala, Venkatesa Ravi, Yu Cao:
Failure diagnosis of asymmetric aging under NBTI. ICCAD 2011: 428-433 - [c6]Hong Luo, Xiaoming Chen, Jyothi Velamala, Yu Wang, Yu Cao, Vikas Chandra, Yuchun Ma, Huazhong Yang:
Circuit-level delay modeling considering both TDDB and NBTI. ISQED 2011: 14-21 - 2010
- [c5]Srivatsan Chellappa, Jia Ni, Xiaoyin Yao, Nathan D. Hindman, Jyothi Velamala, Min Chen, Yu Cao, Lawrence T. Clark:
In-situ characterization and extraction of SRAM variability. DAC 2010: 711-716 - [c4]Evelyn Mintarno, Joëlle Skaf, Rui Zheng, Jyothi Velamala, Yu Cao, Stephen P. Boyd, Robert W. Dutton, Subhasish Mitra:
Optimized self-tuning for circuit aging. DATE 2010: 586-591 - [c3]Jin Sun, Rui Zheng, Jyothi Velamala, Yu Cao, Roman L. Lysecky, Karthik Shankar, Janet Meiling Wang Roveda:
A self-evolving design methodology for power efficient multi-core systems. ICCAD 2010: 264-268 - 2009
- [c2]Rui Zheng, Jyothi Velamala, Vijay Reddy, Varsha Balakrishnan, Evelyn Mintarno, Subhasish Mitra, Srikanth Krishnan, Yu Cao:
Circuit aging prediction for low-power operation. CICC 2009: 427-430 - [c1]Saurabh Sinha, Wei Xu, Jyothi Bhaskarr Velamala, Tawab Dastagir, Bertan Bakkaloglu, Hongbin Yu, Yu Cao:
Enabling resonant clock distribution with scaled on-chip magnetic inductors. ICCD 2009: 103-108
Coauthor Index
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