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Edwin Rijpkema
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2000 – 2009
- 2005
- [j2]Andrei Radulescu, John Dielissen, Santiago González Pestana, Om Prakash Gangwal, Edwin Rijpkema, Paul Wielage, Kees Goossens:
An efficient on-chip NI offering guaranteed services, shared-memory abstraction, and flexible network configuration. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(1): 4-17 (2005) - [c9]Biniam Gebremichael, Frits W. Vaandrager, Miaomiao Zhang, Kees Goossens, Edwin Rijpkema, Andrei Radulescu:
Deadlock Prevention in the Æthereal Protocol. CHARME 2005: 345-348 - [c8]Kees Goossens, John Dielissen, Om Prakash Gangwal, Santiago González Pestana, Andrei Radulescu, Edwin Rijpkema:
A Design Flow for Application-Specific Networks on Chip with Guaranteed Performance to Accelerate SOC Design and Verification. DATE 2005: 1182-1187 - 2004
- [c7]Santiago González Pestana, Edwin Rijpkema, Andrei Radulescu, Kees Goossens, Om Prakash Gangwal:
Cost-Performance Trade-Offs in Networks on Chip: A Simulation-Based Approach. DATE 2004: 764-769 - [c6]Andrei Radulescu, John Dielissen, Kees Goossens, Edwin Rijpkema, Paul Wielage:
An Efficient On-Chip Network Interface Offering Guaranteed Services, Shared-Memory Abstraction, and Flexible Network Configuration. DATE 2004: 878-883 - 2003
- [c5]Edwin Rijpkema, Kees G. W. Goossens, Andrei Radulescu, John Dielissen, Jef L. van Meerbergen, Paul Wielage, Erwin Waterlander:
Trade Offs in the Design of a Router with Both Guaranteed and Best-Effort Services for Networks on Chip. DATE 2003: 10350-10355 - [p1]Kees Goossens, John Dielissen, Jef L. van Meerbergen, Peter Poplavko, Andrei Radulescu, Edwin Rijpkema, Erwin Waterlander, Paul Wielage:
Guaranteeing the Quality of Services in Networks on Chip. Networks on Chip 2003: 61-82 - 2002
- [c4]Ed F. Deprettere, Edwin Rijpkema, Bart Kienhuis:
Translating Imperative Affine Nested Loop Programs into Process Networks. Embedded Processor Design Challenges 2002: 89-111 - 2000
- [j1]Edwin Rijpkema, Ed F. Deprettere, Bart Kienhuis:
Deriving Process Networks from Nested Loop Algorithms. Parallel Process. Lett. 10(2/3): 165-176 (2000) - [c3]Ed F. Deprettere, Edwin Rijpkema, Paul Lieverse, Bart Kienhuis:
High Level Modeling for Parallel Executions of Nested Loop Algorithms. ASAP 2000: 79-91 - [c2]Bart Kienhuis, Edwin Rijpkema, Ed F. Deprettere:
Compaan: deriving process networks from Matlab for embedded signal processing architectures. CODES 2000: 13-17
1990 – 1999
- 1997
- [c1]Edwin Rijpkema, Gerben J. Hekstra, Ed F. Deprettere, Jun Ma:
A strategy for determining a Jacobi specific dataflow processor. ASAP 1997: 53-
Coauthor Index
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