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R. Govindarajan
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- affiliation: ERNET, India
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2020 – today
- 2024
- [c107]Shilpa Babalad
, Shirish K. Shevade
, Matthew Jacob Thazhuthaveetil
, R. Govindarajan
:
Tile Size and Loop Order Selection using Machine Learning for Multi-/Many-Core Architectures. ICS 2024: 388-399 - 2023
- [c106]Ullas A, Rupesh Nasre, R. Govindarajan:
Reduce, Reuse, and Adapt: Accelerating Graph Processing on GPUs. HiPC 2023: 335-346 - 2022
- [c105]Ashwin Prasad, Sampath Rajendra, Kaushik Rajan, R. Govindarajan, Uday Bondhugula:
Treebeard: An Optimizing Compiler for Decision Tree Based ML Inference. MICRO 2022: 494-511 - 2020
- [j29]V. Srividya, R. Govindarajan:
On odd harmonious labelling of even cycles with parallel chords and dragons with parallel chords. Int. J. Comput. Aided Eng. Technol. 13(4): 409-424 (2020)
2010 – 2019
- 2017
- [j28]Adarsh Patil
, Ramaswamy Govindarajan:
HAShCache: Heterogeneity-Aware Shared DRAMCache for Integrated Heterogeneous Systems. ACM Trans. Archit. Code Optim. 14(4): 51:1-51:26 (2017) - [c104]Jayvant Anantpur, R. Govindarajan:
Taming warp divergence. CGO 2017: 50-60 - [i2]Jayvant Anantpur, Nagendra Dwarakanath Gulur, Shivaram Kalyanakrishnan, Shalabh Bhatnagar, R. Govindarajan:
RLWS: A Reinforcement Learning based GPU Warp Scheduler. CoRR abs/1712.04303 (2017) - 2016
- [c103]Nagendra Gulur, R. Govindarajan, Mahesh Mehendale:
MicroRefresh: Minimizing Refresh Overhead in DRAM Caches. MEMSYS 2016: 350-361 - 2015
- [j27]R. Govindarajan, Guang R. Gao:
Author Rebuttal to Rocha et al. "Comments on Minimizing Buffer Requirements under Rate-Optimal Schedule in Regular Dataflow Networks". J. Signal Process. Syst. 81(1): 135-136 (2015) - [c102]Vaivaswatha Nagaraj, R. Govindarajan:
Approximating flow-sensitive pointer analysis using frequent itemset mining. CGO 2015: 225-234 - [c101]Jayvant Anantpur, R. Govindarajan:
PRO: Progress Aware GPU Warp Scheduling Algorithm. IPDPS 2015: 979-988 - [c100]Nagendra Dwarakanath Gulur, Mahesh Mehendale, Ramaswamy Govindarajan:
A Comprehensive Analytical Performance Model of DRAM Caches. ICPE 2015: 157-168 - 2014
- [j26]Martin Kong
, Antoniu Pop, Louis-Noël Pouchet, R. Govindarajan, Albert Cohen, P. Sadayappan:
Compiler/Runtime Framework for Dynamic Dataflow Parallelization of Tiled Programs. ACM Trans. Archit. Code Optim. 11(4): 61:1-61:30 (2014) - [c99]Sreepathi Pai
, R. Govindarajan, Matthew J. Thazhuthaveetil:
Preemptive thread block scheduling with online structural runtime prediction for concurrent GPGPU kernels. PACT 2014: 483-484 - [c98]Jayvant Anantpur, R. Govindarajan:
Taming Control Divergence in GPUs through Control Flow Linearization. CC 2014: 133-153 - [c97]Prasanna Pandit, R. Govindarajan:
Fluidic Kernels: Cooperative Execution of OpenCL Programs on Multiple Heterogeneous Devices. CGO 2014: 273 - [c96]Nagendra Dwarakanath Gulur, Mahesh Mehendale, R. Manikantan, R. Govindarajan:
Bi-Modal DRAM Cache: Improving Hit Rate, Hit Latency and Bandwidth. MICRO 2014: 38-50 - [c95]Nagendra Gulur, Mahesh Mehendale, Raman Manikantan, Ramaswamy Govindarajan:
ANATOMY: an analytical model of memory system performance. SIGMETRICS 2014: 505-517 - [i1]Sreepathi Pai, R. Govindarajan, Matthew J. Thazhuthaveetil:
Preemptive Thread Block Scheduling with Online Structural Runtime Prediction for Concurrent GPGPU Kernels. CoRR abs/1406.6037 (2014) - 2013
- [j25]Mrugesh R. Gajjar, T. V. Sreenivas, R. Govindarajan:
Fast Likelihood Computation in Speech Recognition using Matrices. J. Signal Process. Syst. 70(2): 219-234 (2013) - [c94]Vaivaswatha Nagaraj, R. Govindarajan:
Parallel flow-sensitive pointer analysis by graph-rewriting. PACT 2013: 19-28 - [c93]Sreepathi Pai
, Matthew J. Thazhuthaveetil, R. Govindarajan:
Improving GPGPU concurrency with elastic kernels. ASPLOS 2013: 407-418 - [c92]Jayvant Anantpur, R. Govindarajan:
Runtime dependence computation and execution of loops on heterogeneous systems. CGO 2013: 31:1-31:10 - 2012
- [j24]T. S. Rajesh Kumar, R. Govindarajan, C. P. Ravikumar:
On-chip memory architecture exploration framework for DSP processor-based embedded system on chip. ACM Trans. Embed. Comput. Syst. 11(1): 5:1-5:25 (2012) - [c91]Sreepathi Pai
, R. Govindarajan, Matthew J. Thazhuthaveetil:
Fast and efficient automatic memory management for GPUs using compiler-assisted runtime coherence scheme. PACT 2012: 33-42 - [c90]Sandya S. Mannarswamy, R. Govindarajan:
Reconciling transactional conflicts with compiler's help. CGO 2012: 53-62 - [c89]Raghu Prabhakar, R. Govindarajan, Matthew J. Thazhuthaveetil:
CUDA-For-Clusters: A System for Efficient Execution of CUDA Kernels on Multi-core Clusters. Euro-Par 2012: 415-426 - [c88]Nagendra Dwarakanath Gulur, R. Manikantan, Mahesh Mehendale, R. Govindarajan:
Multiple sub-row buffers in DRAM: unlocking performance and energy improvement opportunities. ICS 2012: 257-266 - [c87]R. Manikantan, Kaushik Rajan, R. Govindarajan:
Probabilistic Shared Cache Management (PriSM). ISCA 2012: 428-439 - 2011
- [j23]R. Manikantan, R. Govindarajan:
Performance Oriented Prefetching Enhancements Using Commit Stalls. J. Instr. Level Parallelism 13 (2011) - [c86]Nagendra Dwarakanath Gulur, R. Manikantan, R. Govindarajan, Mahesh Mehendale:
Row-Buffer Reorganization: Simultaneously Improving Performance and Reducing Energy in DRAMs. PACT 2011: 189-190 - [c85]Sandya Mannarswamy, Ramaswamy Govindarajan:
Making STMs Cache Friendly with Compiler Transformations. PACT 2011: 232-242 - [c84]Rupesh Nasre
, Ramaswamy Govindarajan:
Prioritizing constraint evaluation for efficient points-to analysis. CGO 2011: 267-276 - [c83]R. Manikantan, R. Govindarajan, Kaushik Rajan:
Extended histories: improving regularity and performance in correlation prefetchers. HiPEAC 2011: 67-76 - [c82]R. Manikantan, Kaushik Rajan, R. Govindarajan:
NUcache: An efficient multicore cache organization based on Next-Use distance. HPCA 2011: 243-253 - [c81]Sandya S. Mannarswamy, Ramaswamy Govindarajan:
Variable Granularity Access Tracking Scheme for Improving the Performance of Software Transactional Memory. IPDPS 2011: 455-466 - [c80]Ashwin Prasad, Jayvant Anantpur, R. Govindarajan:
Automatic compilation of MATLAB programs for synergistic execution on heterogeneous processors. PLDI 2011: 152-163 - [c79]Mrugesh R. Gajjar, T. V. Sreenivas, R. Govindarajan:
Fast computation of Gaussian likelihoods using low-rank matrix approximations. SiPS 2011: 322-327 - 2010
- [c78]Sandya S. Mannarswamy, Ramaswamy Govindarajan:
Analyzing cache performance bottlenecks of STM applications and addressing them with compiler's help. PACT 2010: 547-548 - [c77]R. Manikantan, Kaushik Rajan, R. Govindarajan:
NUcache: a multicore cache organization based on next-use distance. PACT 2010: 569-570 - [c76]Sandya Mannarswamy, R. Govindarajan:
Handling Conflicts with Compiler's Help in Software Transactional Memory Systems. ICPP 2010: 482-491 - [c75]Rupesh Nasre
, Ramaswamy Govindarajan:
Points-to Analysis as a System of Linear Equations. SAS 2010: 422-438 - [e1]R. Govindarajan, David A. Padua, Mary W. Hall:
Proceedings of the 15th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, PPOPP 2010, Bangalore, India, January 9-14, 2010. ACM 2010, ISBN 978-1-60558-877-3 [contents]
2000 – 2009
- 2009
- [j22]Kaushik Rajan, Ramaswamy Govindarajan:
A Novel Cache Architecture and Placement Framework for Packet Forwarding Engines. IEEE Trans. Computers 58(8): 1009-1025 (2009) - [c74]Sandya S. Mannarswamy, Ramaswamy Govindarajan, Rishi Surendran:
Region Based Structure Layout Optimization by Selective Data Copying. PACT 2009: 338-347 - [c73]Rupesh Nasre
, Kaushik Rajan, Ramaswamy Govindarajan, Uday P. Khedker:
Scalable Context-Sensitive Points-to Analysis Using Multi-dimensional Bloom Filters. APLAS 2009: 47-62 - [c72]Abhishek Udupa, R. Govindarajan, Matthew J. Thazhuthaveetil:
Software Pipelined Execution of Stream Programs on GPUs. CGO 2009: 200-209 - [c71]Girish B. C., Ramaswamy Govindarajan:
Reducing Buffer Requirements in Core Routers Using Dynamic Buffering. ICCCN 2009: 1-6 - [c70]Abhishek Udupa, R. Govindarajan, Matthew J. Thazhuthaveetil:
Synergistic execution of stream programs on multicores with accelerators. LCTES 2009: 99-108 - 2008
- [j21]V. Santhosh Kumar, Ravi S. Nanjundiah, Matthew J. Thazhuthaveetil, R. Govindarajan:
Impact of message compression on the scalability of an atmospheric modeling application on clusters. Parallel Comput. 34(1): 1-16 (2008) - [c69]Aditya V. Thakur, R. Govindarajan:
Comprehensive path-sensitive data-flow analysis. CGO 2008: 55-63 - [c68]Girish Chandramohan, Ramaswamy Govindarajan:
Improving Performance of Digest Caches in Network Processors. HiPC 2008: 6-17 - [c67]R. Manikantan, R. Govindarajan:
Focused prefetching: performance oriented prefetching based on commit stalls. ICS 2008: 339-348 - [c66]Mrugesh R. Gajjar, R. Govindarajan, T. V. Sreenivas:
Online unsupervised pattern discovery in speech using parallelization. INTERSPEECH 2008: 2458-2461 - [c65]Sudhakar Surendran, Rubin A. Parekhji, R. Govindarajan:
A systematic approach to synthesis of verification test-suites for modular SoC designs. SoCC 2008: 91-96 - [c64]T. S. Rajesh Kumar, C. P. Ravikumar, R. Govindarajan:
Memory Architecture Exploration Framework for Cache Based Embedded SOC. VLSI Design 2008: 553-559 - 2007
- [j20]Rajani Pai, R. Govindarajan:
FEADS: A Framework for Exploring the Application Design Space on Network Processors. Int. J. Parallel Program. 35(1): 1-31 (2007) - [j19]Hongbo Rong, Zhizhong Tang, Ramaswamy Govindarajan, Alban Douillet, Guang R. Gao:
Single-dimension software pipelining for multidimensional loops. ACM Trans. Archit. Code Optim. 4(1): 7 (2007) - [c63]Kaushik Rajan, Ramaswamy Govindarajan, Bharadwaj Amrutur:
Dynamic Cache Placement with Two-level Mapping to Reduce Conflict Misses. PACT 2007: 422 - [c62]Rajesh Vivekanandham, R. Govindarajan:
A Scalable Low Power Store Queue for Large InstructionWindow Processors. PACT 2007: 430 - [c61]T. S. Rajesh Kumar, C. P. Ravikumar, R. Govindarajan:
MODLEX: A Multi Objective Data Layout EXploration Framework for Embedded Systems-on-Chip. ASP-DAC 2007: 492-497 - [c60]K. Shyam, R. Govindarajan:
An Array Allocation Scheme for Energy Reduction in Partitioned Memory Architectures. CC 2007: 32-47 - [c59]Santosh Nagarakatte
, R. Govindarajan:
Register Allocation and Optimal Spill Code Scheduling in Software Pipelined Loops Using 0-1 Integer Linear Programming Formulation. CC 2007: 126-140 - [c58]K. Shyam, R. Govindarajan:
Compiler-Directed Dynamic Voltage Scaling Using Program Phases. HiPC 2007: 233-244 - [c57]S. Govind, R. Govindarajan, Joy Kuri:
Packet Reordering in Network Processors. IPDPS 2007: 1-10 - [c56]Kaushik Rajan, Ramaswamy Govindarajan:
Emulating Optimal Replacement with a Shepherd Cache. MICRO 2007: 445-454 - [c55]Girish B. C., R. Govindarajan:
A Petri Net Model for Evaluating Packet Buffering Strategies in a Network Processor. QEST 2007: 19-30 - [c54]T. S. Rajesh Kumar, C. P. Ravikumar, R. Govindarajan:
MAX: A Multi Objective Memory Architecture eXploration Framework for Embedded Systems-on-Chip. VLSI Design 2007: 527-533 - [p3]R. Govindarajan:
Instruction Scheduling. The Compiler Design Handbook, 2nd ed. 2007: 19 - [p2]Hongbo Rong, R. Govindarajan:
Advances in Software Pipelining. The Compiler Design Handbook, 2nd ed. 2007: 20 - 2006
- [j18]Subash Chandar G., Mahesh Mehendale, R. Govindarajan:
Area and Power Reduction of Embedded DSP Systems using Instruction Compression and Re-configurable Encoding. J. VLSI Signal Process. 44(3): 245-267 (2006) - [c53]Kaushik Rajan, Ramaswamy Govindarajan:
Two-level mapping based cache index selection for packet forwarding engines. PACT 2006: 212-221 - [c52]Rajesh Vivekanandham, Bharadwaj S. Amrutur, R. Govindarajan:
A scalable low power issue queue for large instruction window processors. ICS 2006: 167-176 - [c51]V. Santhosh Kumar, Matthew J. Thazhuthaveetil, R. Govindarajan:
Exploiting programmable network interfaces for parallel query execution in workstation clusters. IPDPS 2006 - 2005
- [j17]Hongbo Yang, Ramaswamy Govindarajan, Guang R. Gao, Ziang Hu:
Improving power efficiency with compiler-assisted cache replacement. J. Embed. Comput. 1(4): 487-499 (2005) - [c50]V. Santhosh Kumar, Matthew J. Thazhuthaveetil, R. Govindarajan:
Offloading Bloom Filter Operations to Network Processor for Parallel Query Processing in Cluster of Workstations. HiPC 2005: 170-179 - [c49]Kaushik Rajan, Ramaswamy Govindarajan:
A heterogeneously segmented cache architecture for a packet forwarding engine. ICS 2005: 71-80 - [c48]S. Govind, R. Govindarajan:
Performance Modeling and Architecture Exploration of Network Processors. QEST 2005: 189-198 - 2004
- [j16]N. P. Manoj, K. V. Manjunath, R. Govindarajan:
CAS-DSM: A Compiler Assisted Software Distributed Shared Memory. Int. J. Parallel Program. 32(2): 77-122 (2004) - [j15]Manjunath Kudlur, R. Govindarajan:
Performance analysis of methods that overcome false sharing effects in software DSMs. J. Parallel Distributed Comput. 64(8): 887-907 (2004) - [c47]Hongbo Rong, Zhizhong Tang, Ramaswamy Govindarajan, Alban Douillet, Guang R. Gao:
Single-Dimension Software Pipelining for Multi-Dimensional Loops. CGO 2004: 163-174 - [c46]Hongbo Rong, Alban Douillet, Ramaswamy Govindarajan, Guang R. Gao:
Code Generation for Single-Dimension Software Pipelining of Multi-Dimensional Loops. CGO 2004: 175-188 - 2003
- [j14]Ramaswamy Govindarajan, Hongbo Yang, José Nelson Amaral, Chihong Zhang, Guang R. Gao:
Minimum Register Instruction Sequencing to Reduce Register Spills in Out-of-Order Issue Superscalar Architectures. IEEE Trans. Computers 52(1): 4-20 (2003) - [c45]A. Radhika Sarma, R. Govindarajan:
An Efficient Web Cache Replacement Policy. HiPC 2003: 12-22 - [c44]R. Achutharaman, R. Govindarajan, G. Hariprakash, Amos Omondi:
Exploiting Java-ILP on a Simultaneous Multi-Trace Instruction Issue (SMTI) Processor. IPDPS 2003: 76 - [c43]Guang R. Gao, Kevin B. Theobald, Ramaswamy Govindarajan, Clement Leung, Ziang Hu, Haiping Wu, Jizhu Lu, Juan del Cuvillo, Adeline Jacquet, Vincent Janot, Thomas L. Sterling:
Programming Models and System Software for Future High-End Computing Systems: Work-in-Progress. IPDPS 2003: 206 - [c42]Adeline Jacquet, Vincent Janot, Clement Leung, Guang R. Gao, Ramaswamy Govindarajan, Thomas L. Sterling:
An Executable Analytical Performance Evaluation Approach for Early Performance Prediction. IPDPS 2003: 268 - [c41]Hongbo Yang, Ramaswamy Govindarajan, Guang R. Gao, Ziang Hu:
Compiler-Assisted Cache Replacement: Problem Formulation and Performance Evaluation. LCPC 2003: 77-92 - [c40]V. V. N. S. Sarvani, R. Govindarajan:
Unified Instruction Reordering and Algebraic Transformations for Minimum Cost Offset Assignment. SCOPES 2003: 270-284 - [c39]T. S. Rajesh Kumar, R. Govindarajan, C. P. Ravikumar:
Optimal Code and Data Layout in Embedded Systems. VLSI Design 2003: 573-578 - 2002
- [j13]R. Govindarajan, Erik R. Altman, Guang R. Gao:
A Theory for Co-Scheduling Hardware and Software Pipelines in ASIPs and Embedded Processors. Des. Autom. Embed. Syst. 6(3): 243-275 (2002) - [j12]Ramaswamy Govindarajan, Guang R. Gao, Palash Desai:
Minimizing Buffer Requirements under Rate-Optimal Schedule in Regular Dataflow Networks. J. VLSI Signal Process. 31(3): 207-229 (2002) - [c38]R. Vinodh Kumar, B. Lakshmi Narayanan, R. Govindarajan:
Dynamic Path Profile Aided Recompilation in a JAVA Just-In-Time Compiler. HiPC 2002: 495-505 - [c37]Hongbo Yang, Ramaswamy Govindarajan, Guang R. Gao, Kevin B. Theobald:
Power-Performance Trade-Offs for Energy-Efficient Architectures: A Quantitative Study. ICCD 2002: 174-179 - [p1]Ramaswamy Govindarajan:
Instruction Scheduling. The Compiler Design Handbook 2002: 631-688 - 2001
- [j11]Ramaswamy Govindarajan, Anand Sivasubramaniam:
Guest Editors' Introduction: Special Issue on Cluster and Network-Based Computing. J. Parallel Distributed Comput. 61(11): 1507-1511 (2001) - [c36]K. V. Manjunath, R. Govindarajan:
Hidden Costs in Avoiding False Sharing in Software DSMs. HiPC 2001: 294-306 - [c35]Subash Chandar G., Mahesh Mehendale, R. Govindarajan:
Area and Power Reduction of Embedded DSP Systems using Instruction Compression and Re-Configurable Encoding. ICCAD 2001: 631-634 - [c34]Ramaswamy Govindarajan, Hongbo Yang, Chihong Zhang, José Nelson Amaral, Guang R. Gao:
Minimum Register Instruction Sequence Problem: Revisiting Optimal Code Generation for DAGs. IPDPS 2001: 26 - 2000
- [j10]Ramaswamy Govindarajan, N. S. S. Narasimha Rao, Erik R. Altman, Guang R. Gao:
Enhanced Co-Scheduling: A Software Pipelining Method Using Modulo-Scheduled Pipeline Theory. Int. J. Parallel Program. 28(1): 1-46 (2000) - [j9]N. Sreraman, R. Govindarajan:
A Vectorizing Compiler for Multimedia Extensions. Int. J. Parallel Program. 28(4): 363-400 (2000) - [c33]Ramaswamy Govindarajan, Erik R. Altman, Guang R. Gao:
A Theory for Software-Hardware Co-Scheduling for ASIPs and Embedded Processors. ASAP 2000: 329-338
1990 – 1999
- 1999
- [c32]Madhavi Gopal Valluri, R. Govindarajan:
Evaluating Register Allocation and Instruction Scheduling Techniques in Out-Of-Order Issue Processors. IEEE PACT 1999: 78-83 - [c31]Chihong Zhang, Ramaswamy Govindarajan, Sean Ryan, Guang R. Gao:
Efficient State-Diagram Construction Methods for Software Pipelining. CC 1999: 153-167 - [c30]V. Janaki Ramanan, Ramaswamy Govindarajan:
Resource Usage Modelling for Software Pipelining. HiPC 1999: 111-119 - [c29]V. Janaki Ramanan, Ramaswamy Govindarajan:
Resource usage models for instruction scheduling: two new models and a classification. International Conference on Supercomputing 1999: 417-424 - [c28]Ramaswamy Govindarajan, Chihong Zhang, Guang R. Gao:
Minimum Register Instruction Scheduling: A New Approach for Dynamic Instruction Issue Processors. LCPC 1999: 70-84 - 1998
- [j8]Erik R. Altman, Ramaswamy Govindarajan, Guang R. Gao:
A Unified Framework for Instruction Scheduling and Mapping for Function Units with Structural Hazards. J. Parallel Distributed Comput. 49(2): 259-293 (1998) - [c27]Madhavi Gopal Valluri, R. Govindarajan:
Modulo-variable expansion sensitive scheduling. HiPC 1998: 334-341 - [c26]Ramaswamy Govindarajan, N. S. S. Narasimha Rao, Erik R. Altman, Guang R. Gao:
An Enhanced Co-Scheduling Method Using Reduced MS-State Diagrams. IPPS/SPDP 1998: 168-175 - [c25]Amod K. Dani, V. Janaki Ramanan, Ramaswamy Govindarajan:
Register-Sensitive Software Pipelining. IPPS/SPDP 1998: 194-198 - [c24]Wlodzimierz M. Zuberek, R. Govindarajan:
Performance bounds for distributed memory multithreaded architectures. SMC 1998: 232-237 - 1997
- [c23]Rad Silvera, Jian Wang, Ramaswamy Govindarajan, Guang R. Gao:
A Register Pressure Sensitive Instruction Scheduler for Dynamic Issue Processors. IEEE PACT 1997: 78-89 - [c22]B. Hari Krishna, Ramaswamy Govindarajan:
Classification and performance evaluation of simultaneous multithreaded architectures. HiPC 1997: 34-39 - [c21]S. Ramesh, R. Lakshmi, R. Govindarajan:
Distributed Shared Memory on IBM SP2. ICPADS 1997: 338-345 - [c20]R. Govindarajan, F. Suciu, Wlodek M. Zuberek:
Timed Petri net models of multithreaded multiprocessor architectures. PNPM 1997: 153-162 - 1996
- [j7]Ramaswamy Govindarajan, Erik R. Altman, Guang R. Gao:
A Framework for Resource-Constrained Rate-Optimal Software Pipelining. IEEE Trans. Parallel Distributed Syst. 7(11): 1133-1149 (1996) - [c19]Ramaswamy Govindarajan, S. Rengarajan:
Buffer allocation in regular dataflow networks: an approach based on coloring circular-arc graphs. HiPC 1996: 419-424 - [c18]Ramaswamy Govindarajan, Erik R. Altman, Guang R. Gao:
Co-Scheduling Hardware and Software Pipelines. HPCA 1996: 52-61 - 1995
- [j6]Ramaswamy Govindarajan, Guang R. Gao:
Rate-optimal schedule for multi-rate DSP computations. J. VLSI Signal Process. 9(3): 211-232 (1995) - [c17]Ramaswamy Govindarajan, Shashank S. Nemawarkar, Philip LeNir:
Design and Performance Evaluation of a Multithreaded Architecture. HPCA 1995: 298-307 - [c16]Erik R. Altman, Guang R. Gao, Ramaswamy Govindarajan:
An Experimental Study of an ILP-based Exact Solution Method for Software Pipelining. LCPC 1995: 16-30 - [c15]Erik R. Altman, Ramaswamy Govindarajan, Guang R. Gao:
Scheduling and Mapping: Software Pipelining in the Presence of Structural Hazards. PLDI 1995: 139-150 - 1994
- [c14]Ramaswamy Govindarajan, Guang R. Gao, Palash Desai:
Minimizing memory requirements in rate-optimal schedules. ASAP 1994: 75-86 - [c13]Ramaswamy Govindarajan, Erik R. Altman, Guang R. Gao:
A Framework for Resource-Constrained Rate-Optimal Software Pipelining. CONPAR 1994: 640-651 - [c12]Ramaswamy Govindarajan, Erik R. Altman, Guang R. Gao:
Minimizing register requirements under resource-constrained rate-optimal software pipelining. MICRO 1994: 85-94 - [c11]Shashank S. Nemawarkar, Ramaswamy Govindarajan, Guang R. Gao, Vinod K. Agarwal:
Performance of Interconnection Network in Multithreaded Architectures. PARLE 1994: 823-826 - 1993
- [j5]R. Govindarajan:
Exception Handlers in Functional Programming Languages. IEEE Trans. Software Eng. 19(8): 826-834 (1993) - [c10]R. Govindarajan, Guang R. Gao:
A novel framework for multi-rate scheduling in DSP applications. ASAP 1993: 77-88 - [c9]Shashank S. Nemawarkar, Ramaswamy Govindarajan, Guang R. Gao, Vinod K. Agarwal:
Analysis of Multithreaded Multiprocessors with Distributed Shared Memory. SPDP 1993: 114-121 - 1992
- [j4]R. Govindarajan, Sheng Yu, V. S. Lakshmanan:
Attempting guards in parallel: A data flow approach to execute generalized guarded commands. Int. J. Parallel Program. 21(4): 225-268 (1992) - [c8]R. Govindarajan:
Software fault-tolerance in functional programming. COMPSAC 1992: 194-199 - [c7]Ramaswamy Govindarajan, Shashank S. Nemawarkar:
A Large Context Multithreaded Architecture. CONPAR 1992: 423-428 - [c6]Guang R. Gao, R. Govindarajan, Prakash Panangaden:
Well-behaved dataflow programs for DSP computation. ICASSP 1992: 561-564 - [c5]Shashank S. Nemawarkar, Ramaswamy Govindarajan, Guang R. Gao, Vinod K. Agarwal:
Performance Evaluation of Latency Tolerant Architectures. ICCI 1992: 183-186 - [c4]Philip LeNir, Ramaswamy Govindarajan, Shashank S. Nemawarkar:
Exploiting instruction-level parallelism: the multithreaded approach. MICRO 1992: 189-192 - [c3]Ramaswamy Govindarajan, Shashank S. Nemawarkar:
SMALL: A Scalable Multithreaded Architecture to Exploit Large Localiy. SPDP 1992: 32-39 - 1991
- [c2]R. Govindarajan, Lifu Guo, Sheng Yu, P. Wang:
ParC project: practical constructs for parallel programming languages. COMPSAC 1991: 183-189 - [c1]R. Govindarajan, Sheng Yu:
Data Flow Implementation of Generalized Guarded Commands. PARLE (1) 1991: 372-389 - 1990
- [j3]R. Govindarajan, Lalit M. Patnaik:
Lenient Execution and Concurrent Execution of Re-Entrant Routines: Efficient Implementation in Data Flow Systems. Comput. J. 33(2): 185-187 (1990)
1980 – 1989
- 1989
- [j2]R. Govindarajan, R. Kumar, D. Kumar, L. M. Patnaik:
PROMIDS: A PROtotype multi-rIng data flow system for functional programming languages. Microprocessing and Microprogramming 26(3): 161-173 (1989) - 1986
- [j1]Lalit M. Patnaik, R. Govindarajan, N. S. Ramadoss:
Design and Performance Evaluation of EXMAN: An EXtended MANchester Data Flow Computer. IEEE Trans. Computers 35(3): 229-244 (1986)
Coauthor Index
aka: Matthew Jacob Thazhuthaveetil
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Privacy notice: By enabling the option above, your browser will contact the API of unpaywall.org to load hyperlinks to open access articles. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Unpaywall privacy policy.
Archived links via Wayback Machine
For web page which are no longer available, try to retrieve content from the of the Internet Archive (if available).
Privacy notice: By enabling the option above, your browser will contact the API of archive.org to check for archived content of web pages that are no longer available. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Internet Archive privacy policy.
Reference lists
Add a list of references from ,
, and
to record detail pages.
load references from crossref.org and opencitations.net
Privacy notice: By enabling the option above, your browser will contact the APIs of crossref.org, opencitations.net, and semanticscholar.org to load article reference information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Crossref privacy policy and the OpenCitations privacy policy, as well as the AI2 Privacy Policy covering Semantic Scholar.
Citation data
Add a list of citing articles from and
to record detail pages.
load citations from opencitations.net
Privacy notice: By enabling the option above, your browser will contact the API of opencitations.net and semanticscholar.org to load citation information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the OpenCitations privacy policy as well as the AI2 Privacy Policy covering Semantic Scholar.
OpenAlex data
Load additional information about publications from .
Privacy notice: By enabling the option above, your browser will contact the API of openalex.org to load additional information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the information given by OpenAlex.
last updated on 2024-08-18 21:52 CEST by the dblp team
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