20th VLSI Design 2007: Bangalore, India

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Plenary Sessions

Session A1: Formal Verification

Session B1: Scheduling for Embedded Processors

Session C1: Architecture and Design

Session D1: RF Circuits

Session A2: Technology Modeling and Simulation

Session B2: Compilation Techniques for Embedded Processors

Session C2: Signal Integrity and Timing Analysis

Session D2: Digital Circuits

Session A3: SOC Test and Verification

Session B3: Dynamic and Runtime Reconfigurable Systems

Session C3: Synthesis and System Level Design

Session D3: Low Power

Session A4: Test Generation and High Level Test

Session B4: System Level Modeling, Estimation and Exploration

Session C4: Power Analysis and Optimization

Session D4: Memory Design