Stop the war!Остановите войну!
for scientists:
default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCID20th VLSI Design 2007: Bangalore, India
- 20th International Conference on VLSI Design (VLSI Design 2007), Sixth International Conference on Embedded Systems (ICES 2007), 6-10 January 2007, Bangalore, India. IEEE Computer Society 2007, ISBN 0-7695-2762-0
Tutorials
- Srivaths Ravi, Stefan Mangard:
Tutorial T1: Designing Secure SoCs. 3 - S. Sundar Kumar Iyer, Vivek Subramanian:
Tutorial T2: Organic Electronics: Technology, Devices, Circuits, and Applications. 4 - Subhomoy Chattopadhyay, Rakesh Patel:
Tutorial T3: Low Power Design Techniques for Nanometer Design Processes - 65nm and Smaller. 5 - Jacob A. Abraham, Daniel G. Saab:
Tutorial T4A: Formal Verification Techniques and Tools for Complex Designs. 6 - Praveen Tiwari, Raj S. Mitra, Manu Chopra, Alok Jain:
Tutorial T4B: Formal Assertion-Based Verification in Industrial Setting. 7 - Nikil D. Dutt
, Kaustav Banerjee, Luca Benini, Kanishka Lahiri, Sudeep Pasricha:
Tutorial 5: SoC Communication Architectures: Technology, Current Practice, Research, and Trends. 8 - Sarma B. K. Vrudhula, Sarvesh Bhardwaj:
Tutorial T6: Robust Design of Nanoscale Circuits in the Presence of Process Variations. 9 - Eric Beyne:
Tutorial T7A: Advanced IC Packaging. 10 - Sanjay Gupta, Taranjit Kukal, Alok Tripathi, Raja Mitra, Ashish Patni, Siddarth Shetty:
Tutorial T7B: RF Analysis and Simulation with Focus on RF SiP Methodology. 11 - Vinod Kathail, Shail Aditya, Craig Gleason, Nagesh Chatekar:
Tutorial T8A: Automated Application Engine Synthesis from C Algorithms. 12 - Samarjit Chakraborty, Abhik Roychoudhury:
Tutorial T8B: Performance Debugging of Complex Embedded Systems. 13 - Puranjoy Bhattacharya:
Tutorial IND1A: NeXperia - A Versatile Configurable Platform for Home and Mobile Computing. 14 - Uma Maheswar Rao, Suneel Sinha, Naveen Shenoy:
Tutorial IND1B: Realtime Operating Systems for Embedded Systems Development. 15 - Parimal Patel:
Tutorial IND2A: Embedded Systems Design with Xilinx Virtex-5 Series FPGA. 16 - C. J. Clark:
Tutorial IND2B: Structured Embedded Configuration and Test. 17
Plenary Sessions
- Wim Roelandts:
Creating a Culture of Innovation. 21-22 - Mark Horowitz:
Scaling, Power and the Future of CMOS. 23 - Sandip Tiwari:
Nanoelectronics Device Technologies: CMOS, Beyond and the Mysterious Case of Ockham's Razor. 24-25 - Ahmad Bahai:
Where Analog meets Digital and Beyond. 26 - Ajith Amerasekera:
Concurrent Optimization of Technology and Design for Nano CMOS. 27 - Alberto L. Sangiovanni-Vincentelli:
Reasoning about the Trends and Challenges of Engineering Design Automation. 28-30 - J. Augusto de Oliveira:
Nexperia Computing Architecture for Connected Consumer Applications. 31 - Roberto Guerrieri:
Convergence of Nanoelectronics and Living Cells: A New Frontier for Diagnostics and Therapy? 32 - René Penning de Vries:
Systems, Nano-technology and SiP. 33
Session A1: Formal Verification
- Zhaohui Fu, Sharad Malik:
Extracting Logic Circuit Structure from Conjunctive Normal Form Descriptions. 37-42 - Shobha Vasudevan, Vinod Viswanath, Jacob A. Abraham:
Efficient Microprocessor Verification using Antecedent Conditioned Slicing. 43-49 - Malay K. Ganai, Akira Mukaiyama, Aarti Gupta, Kazutoshi Wakabayashi:
Synthesizing "Verification Aware" Models: Why and How? 50-56 - Subrat Kumar Panda, Arnab Roy, P. P. Chakrabarti, Rajeev Kumar:
Simulation Based Verification using Temporally Attributed Boolean Logic. 57-62 - Vishnu C. Vimjam, Michael S. Hsiao:
Explicit Safety Property Strengthening in SAT-based Induction. 63-68 - Görschwin Fey, Tim Warode, Rolf Drechsler:
Reusing Learned Information in SAT-based ATPG. 69-76
Session B1: Scheduling for Embedded Processors
- Feihui Li, Guilin Chen, Mahmut T. Kandemir, Ozcan Ozturk, Mustafa Karaköy, Rajaraman Ramanarayanan, Balaji Vaidyanathan:
A Process Scheduler-Based Approach to NoC Power Management. 77-82 - Ranjani Sridharan, Rabi N. Mahapatra:
Analysis of RealTime Embedded Applications in the Presence of a Stochastic Fault Model. 83-88 - Pravanjan Choudhury, P. P. Chakrabarti, Rajeev Kumar:
Online Dynamic Voltage Scaling using Task Graph Mapping Analysis for Multiprocessors. 89-94 - Sayak Ray, Pallab Dasgupta, P. P. Chakrabarti:
A New Pseudo-Boolean Satisfiability based approach to Power Mode Schedulability Analysis. 95-102
Session C1: Architecture and Design
- Balaji Vaidyanathan, Wei-Lun Hung, Feng Wang, Yuan Xie, Narayanan Vijaykrishnan, Mary Jane Irwin:
Architecting Microprocessor Components in 3D Design Space. 103-108 - Sanghoan Chang, Gwan Choi:
Gate-Level Exception Handling Design for Noise Reduction in High-Speed VLSI Circuits. 109-114 - Sanjiv Kumar Mangal, Raghavendra B. Deshmukh, Rahul M. Badghare, Rajendra M. Patrikar:
FPGA Implementation of Low Power Parallel Multiplier. 115-120 - Rohit Pandey, Michael L. Bushnell:
Architecture for Variable-Length Combined FFT, DCT, and MWT Transform Hardware for a Multi-ModeWireless System. 121-126 - Sharath Jayaprakash, Nihar R. Mahapatra:
Partitioned Hybrid Encoding to Minimize On-Chip Energy Dissipation ofWide Microprocessor Buses. 127-134
Session D1: RF Circuits
- Rahim Bagheri, Ahmad Mirzaei, Saeed Chehrazi, Asad A. Abidi:
Architecture and Clock Programmable Baseband of an 800 MHz-6 GHz Software-Defined Wireless Receiver. 135-140 - Vijay Khawshe, Pravin V. Kumar, Renu Rangnekar, Kapil Vyas, Kashi Prabu, Mahabaleshwara, Manish Jain, Navin K. Mishra, Abhijit Abhyankar:
A 2.5Gbps Quad CMOS Transceiver Cell Using Regulated Supply Low Jitter PLL. 141-145 - Shaikh K. Alam:
A 2 GHz Low Power Down-conversion Quadrature Mixer in 0.18-µm CMOS. 146-154 - Jagdish Nayayan Pandey, Sudhir S. Kudva, Bharadwaj Amrutur:
A Low Power Frequency Multiplication Technique for ZigBee Transciever. 150-155 - Debashis Mandal, T. K. Bhattacharyya:
7.95mW 2.4GHz Fully-Integrated CMOS Integer N Frequency Synthesizer. 156-164
Session A2: Technology Modeling and Simulation
- Feng Wang, Yuan Xie, R. Rajaraman, Balaji Vaidyanathan:
Soft Error Rate Analysis for Combinational Logic Using An Accurate Electrical Masking Model. 165-170 - Hamed Aminzadeh, Mohammad Danaie, Reza Lotfi:
Design of Two-Stage Miller-Compensated Amplifiers Based on an Optimized Settling Model. 171-176 - Yogesh Singh Chauhan, François Krummenacher, Renaud Gillon, Benoit Bakeroot, Michel J. Declercq, Adrian M. Ionescu:
A New Charge based Compact Model for Lateral Asymmetric MOSFET and its application to High Voltage MOSFET Modeling. 177-182 - Deblina Sarkar, Samiran Ganguly, Deepanjan Datta, A. Ananda Prasad Sarab, Sudeb Dasgupta:
Modeling of Leakages in Nano-Scale DG MOSFET to Implement Low Power SRAM: A Device/Circuit Co-Design. 183-188 - Mamidala Jagadesh Kumar, Vivek Venkataraman, Susheel Nawal:
Analytical Drain Current Model of Nanoscale Strained-Si/SiGe MOSFETs for Analog Circuit Simulation. 189-194 - Elias Kougianos, Saraju P. Mohanty:
Metrics to Quantify Steady and Transient Gate Leakage in Nanoscale Transistors: NMOS vs. PMOS Perspective. 195-200 - Huiying Yang, Ranga Vemuri:
Efficient Symbolic Sensitivity based Parasitic-Inclusive Optimization in Layout Aware Analog Circuit Synthesis. 201-206 - Chaitanya Sathe, Santanu Mahapatra:
Modeling and Analysis of Noise Margin in SET Logic. 207-214
Session B2: Compilation Techniques for Embedded Processors
- Soumyaroop Roy, Srinivas Katkoori, Nagarajan Ranganathan:
A Compiler Based Leakage Reduction Technique by Power-Gating Functional Units in Embedded Microprocessors. 215-220 - Taylan Yemliha, Guangyu Chen, Ozcan Ozturk, Mahmut T. Kandemir, Vijay Degalahal:
Compiler-Directed Code Restructuring for Operating with Compressed Arrays. 221-226 - Mahmut T. Kandemir, Ozcan Ozturk, Vijay Degalahal:
Enhancing Locality in Two-Dimensional Space through Integrated Computation and Data Mappings. 227-232 - Neeraj Goel, Anshul Kumar, Preeti Ranjan Panda:
Power Reduction in VLIW Processor with Compiler Driven Bypass Network. 233-238 - Rakesh Nalluri, Rohan Garg, Preeti Ranjan Panda:
Customization of Register File Banking Architecture for Low Power. 239-244 - Sameer D. Sahasrabuddhe, Hakim Raja, Kavi Arya, Madhav P. Desai:
AHIR: A Hardware Intermediate Representation for Hardware Generation from High-level Programs. 245-250 - Liping Xue, Mahmut T. Kandemir, Guilin Chen, Feihui Li, Ozcan Ozturk, Rajaraman Ramanarayanan, Balaji Vaidyanathan:
Locality-Aware Distributed Loop Scheduling for Chip Multiprocessors. 251-258
Session C2: Signal Integrity and Timing Analysis
- Ashish Dobhal, Vishal Khandelwal, Ankur Srivastava:
Efficient and Accurate Statistical Timing Analysis for Non-Linear Non-Gaussian Variability With Incremental Attributes. 259-264 - Srinath R. Naidu:
Speeding up Monte-Carlo Simulation for Statistical Timing Analysis of Digital Integrated Circuits. 265-270 - Vineet Wason, Rajeev Murgai, William W. Walker:
An Efficient Uncertainty- and Skew-aware Methodology for Clock Tree Synthesis and Analysis. 271-277 - Ratnakar Goyal, Sachin Shrivastava, Harindranath Parameswaran, Parveen Khurana:
Improved First-Order Parameterized Statistical Timing Analysis for Handling Slew and Capacitance Variation. 278-282 - Amit Kumar, Krishnendu Chakrabarty, Chunduri Rama Mohan:
An ECO Technique for Removing Crosstalk Violations in Clock Networks. 283-288 - Boyan Semerdjiev, Dimitrios Velenis:
Optimal Crosstalk Shielding Insertion along On-Chip Interconnect Trees. 289-294 - Suchismita Roy, P. P. Chakrabarti, Pallab Dasgupta:
Bounded Delay Timing Analysis Using Boolean Satisfiability. 295-302
Session D2: Digital Circuits
- Keivan Navi, Omid Kavehei, Mahnoush Rouholamini, Amir Sahafi, Shima Mehrabi:
A Novel CMOS Full Adder. 303-307 - Roshan Weerasekera, Dinesh Pamunuwa, Li-Rong Zheng, Hannu Tenhunen:
Delay-Balanced Smart Repeaters for On-Chip Global Signaling. 308-313 - Jon Alfredsson, Snorre Aunet, Bengt Oelmann:
Small Fan-in Floating-Gate Circuits with Application to an Improved Adder Structure. 314-317 - Gongqiong Li, Zhaolin Li:
Design of A Fully Pipelined Single-Precision Multiply-Add-Fused Unit. 318-323 - Sreehari Veeramachaneni, Kirthi M. Krishna, Lingamneni Avinash, Reddy Puppala Sreekanth, M. B. Srinivas:
Novel Architectures for High-Speed and Low-Power 3-2, 4-2 and 5-2 Compressors. 324-329 - Claas Cornelius, Frank Grassert, Siegmar Koppe, Dirk Timmermann:
Deep Submicron Technology: Opportunity or Dead End for Dynamic Circuit Techniques. 330-338
Session A3: SOC Test and Verification
- Sandeep Jain, Jais Abraham, Srinivas Kumar Vooka, Sumant Kale, Amit Dutta, Rubin A. Parekhji:
Enhancements in Deterministic BIST Implementations for Improving Test of Complex SOCs. 339-344 - Kedarnath J. Balakrishnan:
Efficient Scan-Based BIST Using Multiple LFSRs and Dictionary Coding. 345-350 - V. R. Devanathan, C. P. Ravikumar, V. Kamakoti:
Reducing SoC Test Time and Test Power in Hierarchical Scan Test : Scan Architecture and Algorithms. 351-356 - Rajamani Sethuram, Seongmoon Wang, Srimat T. Chakradhar, Michael L. Bushnell:
Zero Cost Test Point Insertion Technique for Structured ASICs. 357-363 - Subir K. Roy, Rubin A. Parekhji:
Modeling Techniques for Formal Verification of BIST Controllers and Their Integration into SOC Designs. 364-372
Session B3: Dynamic and Runtime Reconfigurable Systems
- Kenji Asano, Junji Kitamichi, Kenichi Kuroda:
Proposal of Dynamic Module Library for System Level Modeling and Simulation of Dynamically Reconfigurable Systems. 373-378 - Senthil Kumar Lakshmanan, Peter Tawdross, Andreas König:
Towards Generic On-the-Fly Reconfigurable Sensor Electronics for Embedded System- First Measurement Results of Reconfigurable Folded. 379-384 - Jorgen Peddersen, Sri Parameswaran:
Energy Driven Application SelfAdaptation. 385-390 - Phillip H. Jones, Young H. Cho, John W. Lockwood:
Dynamically Optimizing FPGA Applications by Monitoring Temperature and Workloads. 391-400
Session C3: Synthesis and System Level Design
- Dhiren M. Parmar, Monalisa Sarma, Debasis Samanta:
A Novel Approach to Domino Circuit Synthesis. 401-406 - K. Najeeb, Karthik Gururaj, V. Kamakoti, Vivekananda M. Vedula:
Controllability-driven Power Virus Generation for Digital Circuits. 407-412 - Fu-Chiung Cheng, Shu-Ming Chang, Chi-Huam Shieh:
Detection and Generation of Self-Timed Pipelines from High Level Specifications. 413-418 - Balasubramanian Sethuraman, Ranga Vemuri:
A Force-directed Approach for Fast Generation of Efficient Multi-Port NoC Architectures. 419-426
Session D3: Low Power
- Hendrik F. Hamann, Alan J. Weger, James A. Lacey, Zhigang Hu, Pradip Bose, Erwin B. Cohen, Jamil A. Wakil:
Temperature-limited microprocessors: Measurements and design implications. 427-432 - Qianneng Zhou, Fengchang Lai, Yongsheng Wang:
On-Chip Voltage Down Converter Based on Moderate Inversion for Low- Power VLSI Chips. 433-438 - Yuanlin Lu, Vishwani D. Agrawal:
Statistical Leakage and Timing Optimization for Submicron Process Variation. 439-444 - Akepati Sravan, Sujan Kundu, Ajit Pal:
Low Power Sensor Node for a Wireless Sensor Network. 445-450 - Yijun Liu, Zhenkun Li, Pinghua Chen, Guangcong Liu:
Power-Efficient Asynchronous Design. 451-458
Session A4: Test Generation and High Level Test
- Sudarshan Bahukudumbi, Krishnendu Chakrabarty:
Test-Length Selection and TAM Optimization for Wafer-Level, Reduced Pin-Count Testing of Core-Based Digital SoCs. 459-464 - Sreekumar V. Kodakara, Deepak Mathaikutty, Ajit Dingankar, Sandeep K. Shukla, David J. Lilja:
Model Based Test Generation for Microprocessor Architecture Validation. 465-472 - Nitin Yogi, Vishwani D. Agrawal:
Spectral RTL Test Generation for Microprocessors. 473-478 - Hafizur Rahaman, Jimson Mathew, Dhiraj K. Pradhan:
Constant Function Independent Test Set for Fault Detection in Bit Parallel Multipliers in GF(2^m). 479-484 - Suresh Kumar Devanathan, Michael L. Bushnell:
Test Pattern Generation Using Modulation by Haar Wavelets and Correlation for Sequential BIST. 485-491 - Kalyana R. Kantipudi, Vishwani D. Agrawal:
A Reduced Complexity Algorithm for Minimizing N-Detect Tests. 492-497 - Irith Pomeranz, Sudhakar M. Reddy:
Equivalence and Dominance Relations Between Fault Pairs and Their Use in Fault Pair Collapsing for Fault Diagnosis. 498-503 - Loganathan Lingappan, Vijay Gangaram, Niraj K. Jha:
Fast Enhancement of Validation Test Sets to Improve Stuck-at Fault Coverage for RTL circuits. 504-512
Session B4: System Level Modeling, Estimation and Exploration
- Nikhil Bansal, Kanishka Lahiri, Anand Raghunathan:
Automatic Power Modeling of Infrastructure IP for System-on-Chip Power Analysis. 513-520 - Ashish Mathur, Sourav Roy, Rajat Bhatia, Arup Chakraborty, Vijay Bhargava, Jatin Bhartia:
JouleQuest: An Accurate Power Model for the StarCore DSP Platform. 521-526 - T. S. Rajesh Kumar, C. P. Ravikumar, R. Govindarajan:
MAX: A Multi Objective Memory Architecture eXploration Framework for Embedded Systems-on-Chip. 527-533 - Wei-Tsun Sun, Zoran Salcic:
Modeling RTOS for Reactive Embedded Systems. 534-539 - Gautam Hazari, Madhav P. Desai, H. Kasture:
On the Impact of Address Space Assignment on Performance in Systems-on-Chip. 540-545 - Masoud Daneshtalab, A. Pedram, Mohammad Hossein Neishaburi, Mohammad Riazati, Ali Afzali-Kusha, Siamak Mohammadi:
Distributing Congestions in NoCs through a Dynamic Routing Algorithm based on Input and Output Selections. 546-550 - Nagaraju Pothineni, Anshul Kumar, Kolin Paul:
Application Specific Datapath Extension with Distributed I/O Functional Units. 551-558
Session C4: Power Analysis and Optimization
- Aseem Gupta, Nikil D. Dutt, Fadi J. Kurdahi, Kamal S. Khouri, Magdy S. Abadir:
STEFAL: A System Level Temperature- and Floorplan-Aware Leakage Power Estimator for SoCs. 559-564 - Subramanian Rajagopalan, Shabbir H. Batterywala:
A 3-dimensional FEM Based Resistance Extraction. 565-570 - Ashish Dobhal, Vishal Khandelwal, Azadeh Davoodi, Ankur Srivastava:
Variability Driven Joint Leakage-Delay Optimization Through Gate Sizing with Provabale Convergence. 571-576 - Saraju P. Mohanty, Elias Kougianos:
Simultaneous Power Fluctuation and Average Power Minimization during Nano-CMOS Behavioral Synthesis. 577-582 - Ashesh Rastogi, Wei Chen, Alodeep Sanyal, Sandip Kundu:
An Efficient Technique for Leakage Current Estimation in Sub 65nm Scaled CMOS Circuits Based on Loading Effect. 583-588 - Sarvesh Bhardwaj, Sarma B. K. Vrudhula:
A Fast and Accurate approach for Full Chip Leakage Analysis of Nano-scale circuits considering Intra-die Correlations. 589-594 - Anupam Chattopadhyay, Diandian Zhang, David Kammler, Ernst Martin Witte:
Power-efficient Instruction Encoding Optimization for Embedded Processors. 595-600 - Nenggan Zheng, Zhaohui Wu, Man Lin, Qijia Wang:
Interpreting and Extending an Analytical Battery Model Using an Iterative Computation Method. 601-608
Session D4: Memory Design
- Masaaki Iijima, Masayuki Kitamura, Masahiro Numa, Akira Tada, Takashi Ipposhi:
Ultra Low Voltage Operation with Bootstrap Scheme for Single Power Supply SOI-SRAM. 609-614 - Qikai Chen, Arjun Guha, Kaushik Roy:
An Accurate Analytical SNM Modeling Technique for SRAMs Based on Butterworth Filter Function. 615-620 - Sayeed A. Badrudduza, Giby Samson, Lawrence T. Clark:
LCSRAM: A Leakage Controlled Six-transistor Static Random Access Memory Cell with Intrinsically High Read Stability. 621-626 - Lava P. Kumar, Baquer Mazhari:
Optimum Supply Voltages for Minimization of Leakage Currents in SRAM in Stand-by Mode. 627-631 - Duk-Hyung Lee, Dong-Kone Kwak, Kyeong-Sik Min:
Comparative Study on SRAMs for Suppressing Both Oxide-Tunneling Leakage and Subthreshold Leakage in Sub-70-nm Leakage Dominant VLSIs. 632-637 - K. R. Viveka, Abhilasha Kawle, Bharadwaj Amrutur:
Low Power Pipelined TCAM Employing Mismatch Dependent Power Allocation Technique. 638-646
Session A5: Emerging Technology
- Tao Xu, Krishnendu Chakrabarty, Fei Su:
Defect-Aware Synthesis of Droplet-Based Microfluidic Biochips. 647-652 - Jyi-Tsong Lin, Yi-Chuen Eng, Tai-Yi Lee, Kao-Cheng Lin:
Analysis of Si-body thickness variation for a new 40 nm gate length bFDSOI. 653-656 - Daniel Mazor, Michael L. Bushnell, David J. Mulligan, Richard J. Blaikie:
Fault Models and Device Yield of a Large Population of Room Temperature Operation Single-Electron Transistors. 657-664 - Rajiv V. Joshi, Keunwoo Kim, Richard Q. Williams, Edward J. Nowak, Ching-Te Chuang:
A High-Performance, Low Leakage, and Stable SRAM Row-Based Back-Gate Biasing Scheme in FinFET Technology. 665-672
Session B5: Architecture Enhancements for Embedded Processors
- Jiajin Tu, Jian Chen, Lizy K. John:
Hardware Efficient Piecewise Linear Branch Predictor. 673-678 - Rajamani Sethuram, Omar I. Khan, Hari Vijay Venkatanarayanan, Michael L. Bushnell:
A Neural Net Branch Predictor to Reduce Power. 679-684 - Soumyajit Dey, Monu Kedia, Niket Agarwal, Anupam Basu:
Embedded Support Vector Machine : Architectural Enhancements and Evaluation. 685-690 - Asral Bahari, Tughrul Arslan, Ahmet T. Erdogan:
Interframe Bus Encoding Technique for Low Power Video Compression. 691-698
Session C5: Process Variation and Reliability
- Swarup Bhunia, Saibal Mukhopadhyay, Kaushik Roy:
Process Variations and Process-Tolerant Design. 699-704 - Debayan Bhaduri, Sandeep K. Shukla, Paul S. Graham, Maya B. Gokhale:
Scalable techniques and tools for reliability analysis of large circuits. 705-710 - Maryam Ashouei, Muhammad Mudassar Nisar, Abhijit Chatterjee, Adit D. Singh, Abdulkadir Utku Diril:
Probabilistic Self-Adaptation of Nanoscale CMOS Circuits: Yield Maximization under Increased Intra-Die Variations. 711-716 - Krishnan Ramakrishnan, Sivaprakasam Suresh, Narayanan Vijaykrishnan, Mary Jane Irwin:
Impact of NBTI on FPGAs. 717-722 - Xiangning Yang, Eric F. Weglarz, Kewal K. Saluja:
On NBTI Degradation Process in Digital Logic Circuits. 723-730
Session D5: Hardware Architectures
- Matteo Giaconia, Marco Macchetti, Francesco Regazzoni, Kai Schramm:
Area and Power Efficient Synthesis of DPA-Resistant Cryptographic S-Boxes. 731-737 - Kiran K. Gunnam, Gwan S. Choi, Mark B. Yeary:
A Parallel VLSI Architecture for Layered Decoding for Array LDPC Codes. 738-743 - Zahid Khan, Tughrul Arslan, John S. Thompson, Ahmet T. Erdogan:
Low Power Implementation for Minimum Norm Sorting and Block Upper Tri-angularization of Matrices used in MIMO Wireless Systems. 744-749 - M. Sudhakar, Ramachandruni Venkata Kamala, M. B. Srinivas:
A Unified, Reconfigurable Architecture for Montgomery Multiplication in Finite Fields GF(p) and GF(2^n). 750-755 - Jong Hun Han, Ahmet T. Erdogan, Tughrul Arslan:
A Power and Area Efficient Maximum Likelihood Detector Implementation for High Throughput MIMO Systems. 756-762
Session A6: Analog Test, Delay Test, and Test Power
- Gefu Xu, Adit D. Singh:
Delay Test Scan Flip-Flop: DFT for High Coverage Delay Testing. 763-768 - Kim T. Le, Dong Hyun Baik, Kewal K. Saluja:
Test Time Reduction to Test for Path-Delay Faults using Enhanced Random-Access Scan. 769-774 - Jeffrey Ayres, Michael L. Bushnell:
Analog Circuit Testing Using Auto Regressive Moving Average Models. 775-780 - Yoshinobu Higami, Kewal K. Saluja, Hiroshi Takahashi, Yuzo Takamatsu:
Fault Coverage and Fault Efficiency of Transistor Shorts using Gate-Level Simulation and Test Generation. 781-786 - Satish Yada, Bharadwaj S. Amrutur, Rubin A. Parekhji:
Modified Stability Checking for On-line Error Detection. 787-792 - Santiago Remersaro, Xijiang Lin, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski:
Low Shift and Capture Power Scan Tests. 793-798 - Irith Pomeranz, Sudhakar M. Reddy:
Functional Broadside Tests with Different Levels of Reachability. 799-804 - Edward Flanigan, Rajsekhar Adapa, Hailong Cui, Michael Laisne, Spyros Tragoudas, Tsvetomir Petrov:
Function-based ATPG for Path Delay Faults using the Launch-Off-Capture Scan Architecture. 805-812
Session B6: Application-Specific Custom Architectures
- Rahul Jain, Preeti Ranjan Panda:
Memory Architecture Exploration for Power-Efficient 2D-Discrete Wavelet Transform. 813-818 - Himanshu Patel, Sanjay Trivedi, R. Neelkanthan, V. R. Gujraty:
A Robust UART Architecture Based on Recursive Running Sum Filter for Better Noise Performance. 819-823 - Rupak Samanta, Rabi N. Mahapatra:
An Enhanced CAM Architecture to Accelerate LZW Compression Algorithm. 824-829 - Wei-Feng He, Meng-Lian Zhao, Chi-Ying Tsui, Zhi-Gang Mao:
A Scalable Frame-Level Pipelined Architecture for FSBM Motion Estimation. 830-835 - Chitranjan K. Singh, Sushma Honnavara Prasad, Poras T. Balsara:
VLSI Architecture for Matrix Inversion using Modified Gram-Schmidt based QR Decomposition. 836-841 - Debdeep Mukhopadhyay, Pallavi Joshi, Dipanwita Roy Chowdhury:
An Efficient Design of Cellular Automata Based Cryptographically Robust One-Way Function. 842-853 - V. Amudha, B. Venkataramani, R. Vinoth Kumar, S. Ravishankar:
SOC Implementation of HMM Based Speaker Independent Isolated Digit Recognition System. 848-853 - Karthik Baddam, Mark Zwolinski:
Evaluation of Dynamic Voltage and Frequency Scaling as a Differential Power Analysis Countermeasure. 854-862
Session C6: Physical Design and Modeling
- Gaurav Trivedi, Madhav P. Desai, H. Narayanan:
Parallelization of DC Analysis through Multiport Decomposition. 863-868 - Gaurav Trivedi, Sumit Punglia, H. Narayanan:
Application of DC Analyzer to Combinatorial Optimization Problems. 869-874 - Debjit Sinha, Jianfeng Luo, Subramanian Rajagopalan, Shabbir H. Batterywala, Narendra V. Shenoy, Hai Zhou:
Impact of Modern Process Technologies on the Electrical Parameters of Interconnects. 875-880 - Ganesh Venkataraman, Jiang Hu:
A Placement Methodology for Robust Clocking. 881-886 - Sankar P. Debnath, Ganesh P. Kumar, Sukumar Jairam:
Calibration Based Methods for Substrate Modeling and Noise Analysis for Mixed-Signal SoCsc. 887-892 - Pritha Banerjee, Susmita Sur-Kolay, Arijit Bishnu:
Floorplanning in Modern FPGAs. 893-898 - Jin-Tai Yan, Bo-Yi Chiang:
Timing-Constrained Yield-Driven Wiring Reconstruction for Critical Area Minimization. 899-906
Session D6: Analog Techniques
- Reid R. Harrison, Paul T. Watkins, Ryan J. Kier, Daniel J. Black, Robert O. Lovejoy, Richard A. Normann, Florian Solzbacher:
Design and Testing of an Integrated Circuit for Multi-Electrode Neural Recording. 907-912 - S. M. Rezaul Hasan:
A PMOS-diode Differential Body-driven Offset compensated 0.5V. 913-918 - U. K. Vijay, Bharadwaj Amrutur:
Continuous Time Sigma Delta Modulator Employing a Novel Comparator Architecture. 919-924 - Sanjay Kumar Wadhwa, Deeya Muhury, Krishna Thakur:
Programmable Digital Frequency Multiplier. 925-928 - Pradipta Patra, Amit Patra, Debaprasad Kastha:
On-chip implementation of a multi-output voltage regulator based on single inductor Buck Converter topology. 935-940 - Shantanu A. Bhalerao, Abhishek V. Chaudhary, Rajendra M. Patrikar:
A CMOS Low Voltage Charge Pump. 941-946
a service of 
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-04-15 20:32 CEST by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
