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ORCIDDATE 2018: Dresden, Germany
- Jan Madsen, Ayse K. Coskun:
2018 Design, Automation & Test in Europe Conference & Exhibition, DATE 2018, Dresden, Germany, March 19-23, 2018. IEEE 2018, ISBN 978-3-9819263-0-9 - Sung Kim
, Patrick Howe, Thierry Moreau, Armin Alaghi, Luis Ceze, Visvesh Sathe:
MATIC: Learning around errors for efficient low-voltage neural network accelerators. 1-6 - Junki Park, Jaeha Kung, Wooseok Yi, Jae-Joon Kim:
Maximizing system performance by balancing computation loads in LSTM accelerators. 7-12 - Xiaoming Chen, Danny Z. Chen, Xiaobo Sharon Hu:
moDNN: Memory optimal DNN training on GPUs. 13-18 - Dimitrios Stamoulis, Ermao Cai, Da-Cheng Juan, Diana Marculescu:
HyperPower: Power- and memory-constrained hyper-parameter optimization for neural networks. 19-24 - Hsuan Hsiao, Jason Helge Anderson:
Sensei: An area-reduction advisor for FPGA high-level synthesis. 25-30 - Shantanu Dutt, Ouwen Shi:
A fast and effective lookahead and fractional search based scheduling algorithm for high-level synthesis. 31-36 - Samridhi Bansal, Hsuan Hsiao, Tomasz S. Czajkowski, Jason Helge Anderson:
High-level synthesis of software-customizable floating-point cores. 37-42 - Eugene Goldberg, Matthias Güdemann, Daniel Kroening, Rajdeep Mukherjee:
Efficient verification of multi-property designs (The benefit of wrong assumptions). 43-48 - Tobias Seufert, Christoph Scholl:
Combining PDR and reverse PDR for hardware model checking. 49-54 - Mohammad Rahmani Fadiheh, Joakim Urdahl, Srinivasa Shashank Nuthakki, Subhasish Mitra, Clark W. Barrett, Dominik Stoffel, Wolfgang Kunz:
Symbolic quick error detection using symbolic initial state for pre-silicon verification. 55-60 - Lihao Liang, Paul E. McKenney, Daniel Kroening, Tom Melham:
Verification of tree-based hierarchical read-copy update in the Linux kernel. 61-66 - Jingweijia Tan, Kaige Yan:
HVSM: Hardware-variability aware streaming processors' management policy in GPUs. 67-72 - Srinivasa Reddy Punyala, Theodoros Marinakis, Arash Komaee, Iraklis Anagnostopoulos:
Throughput optimization and resource allocation on GPUs under multi-application execution. 73-78 - Zhaoying Li, Lei Ju, Hongjun Dai, Xin Li, Mengying Zhao, Zhiping Jia:
Set variation-aware shared LLC management for CPU-GPU heterogeneous architecture. 79-84 - Amin Rezaei, Yuanqi Shen, Shuyu Kong, Jie Gu, Hai Zhou:
Cyclic locking and memristor-based obfuscation against CycSAT and inside foundry attacks. 85-90 - Grace Li Zhang, Bing Li, Bei Yu, David Z. Pan, Ulf Schlichtmann:
TimingCamouflage: Improving circuit security against counterfeiting by unconventional timing. 91-96 - Satwik Patnaik, Nikhil Rangarajan, Johann Knechtel, Ozgur Sinanoglu, Shaloo Rakheja:
Advancing hardware security using polymorphic and stochastic spin-hall effect devices. 97-102 - Manu Komalan, Oh Hyung Rock, Matthias Hartmann, Sushil Sakhare, Christian Tenllado, José Ignacio Gómez, Gouri Sankar Kar, Arnaud Furnémont, Francky Catthoor, Sophiane Senni, David Novo, Abdoulaye Gamatié, Lionel Torres:
Main memory organization trade-offs with DRAM and STT-MRAM options based on gem5-NVMain simulation frameworks. 103-108 - Bonan Yan, Fan Chen, Yaojun Zhang, Chang Song, Hai Li, Yiran Chen:
Exploring the opportunity of implementing neuromorphic computing systems with spintronic devices. 109-112 - Anteneh Gebregiorgis, Rajendra Bishnoi, Mehdi Baradaran Tahoori:
Spintronic normally-off heterogeneous system-on-chip design. 113-118 - Wang Kang, Xing Chen, Daoqian Zhu, Sai Li, Yangqi Huang, Youguang Zhang, Weisheng Zhao:
Magnetic skyrmions for future potential memory and logic applications: Alternative information carriers. 119-124 - Seyedhamidreza Motaman, Mohammad Nasim Imtiaz Khan, Swaroop Ghosh:
Novel application of spintronics in computing, sensing, storage and cybersecurity. 125-130 - Qi An, Sébastien Le Beux, Ian O'Connor, Jacques-Olivier Klein:
Large scale, high density integration of all spin logic. 131-136 - Mathias Soeken, Thomas Häner, Martin Roetteler:
Programming quantum computers using design automation. 137-146 - Ali Pahlevan, Yasir Mahmood Qureshi, Marina Zapater, Andrea Bartolini, Davide Rossi, Luca Benini, David Atienza:
Energy proportionality in near-threshold computing servers and cloud data centers: Consolidating or Not? 147-152 - Ye Tian, Qian Zhang, Ting Wang, Qiang Xu:
Lookup table allocation for approximate computing with memory under quality constraints. 153-158 - Yun Long, Xueyuan She, Saibal Mukhopadhyay:
Accelerating biophysical neural network simulation with region of interest based approximation. 159-164 - Jinghan Zhang, Hamed Tabkhi, Gunar Schirner:
DS-DSE: Domain-specific design space exploration for streaming applications. 165-170 - Junlong Zhou, Tongquan Wei, Mingsong Chen, Xiaobo Sharon Hu, Yue Ma, Gongxuan Zhang, Jianming Yan:
Variation-aware task allocation and scheduling for improving reliability of real-time MPSoCs. 171-176 - Jianmin Qian, Jian Li, Ruhui Ma:
Topology-aware virtual resource management for heterogeneous multicore systems. 177-182 - Heechun Park, Taewhan Kim:
Structure optimizations of neuromorphic computing architectures for deep neural network. 183-188 - Jiajun Li, Guihai Yan, Wenyan Lu, Shuhao Jiang, Shijun Gong, Jingya Wu, Xiaowei Li:
CCR: A concise convolution rule for sparse neural network accelerators. 189-194 - Thomas Haine, Johan Segers, Denis Flandre, David Bol:
Gradient importance sampling: An efficient statistical extraction methodology of high-sigma SRAM dynamic characteristics. 195-200 - Daniel Kraak, Innocent Agbo, Mottaqiallah Taouil, Said Hamdioui, Pieter Weckx, Stefan Cosemans, Francky Catthoor:
Degradation analysis of high performance 14nm FinFET SRAM. 201-206 - Saba Ahmadian, Farhad Taheri, Mehrshad Lotfi, Maryam Karimi, Hossein Asadi:
Investigating power outage effects on reliability of solid-state drives. 207-212 - Jiankang Ren, Ran Bi, Xiaoyan Su, Qian Liu, Guowei Wu, Guozhen Tan:
Workload-aware harmonic partitioned scheduling for probabilistic real-time systems. 213-218 - Leandro Soares Indrusiak, Alan Burns, Borislav Nikolic:
Buffer-aware bounds to multi-point progressive blocking in priority-preemptive NoCs. 219-224 - Monowar Hasan, Sibin Mohan, Rodolfo Pellizzoni, Rakesh B. Bobba:
A design-space exploration for allocating security tasks in multicore real-time systems. 225-230 - Thanh-Dat Nguyen, Yassine Ouhammou, Emmanuel Grolleau, Julien Forget, Claire Pagetti, Pascal Richard:
Design and analysis of semaphore precedence constraints: A model-based approach for deterministic communications. 231-236 - Houxiang Ji, Linghao Song, Li Jiang, Hai Helen Li, Yiran Chen:
ReCom: An efficient resistive accelerator for compressed deep neural networks. 237-240 - Jingyang Zhu, Jingbo Jiang, Xizi Chen, Chi-Ying Tsui:
SparseNN: An energy-efficient neural network accelerator exploiting input and output sparsity. 241-244 - Jacob R. Stevens, Yue Du, Vivek Kozhikkott, Anand Raghunathan:
ACCLIB: Accelerators as libraries. 245-248 - Isaar Ahmad, Sanjog Patil, Smruti R. Sarangi:
HPXA: A highly parallel XML parser. 249-252 - Seyed Morteza Nabavinejad, Xin Zhan, Reza Azimi, Maziar Goudarzi, Sherief Reda:
QoR-aware power capping for approximate big data processing. 253-256 - Kai Neubauer, Philipp Wanko, Torsten Schaub, Christian Haubelt:
Exact multi-objective design space exploration using ASPmT. 257-260 - Diego G. Tomé, Paulo C. Santos, Luigi Carro, Eduardo C. de Almeida, Marco A. Z. Alves:
HIPE: HMC instruction predication extension applied on database processing. 261-264 - Sarath Mohanachandran Nair, Rajendra Bishnoi, Mehdi Baradaran Tahoori:
Parametric failure modeling and yield analysis for STT-MRAM. 265-268 - Martin Schoeberl:
One-way shared memory. 269-272 - Rui Xu, Xi Jin, Linfeng Tao, Shuaizhi Guo, Zikun Xiang, Teng Tian:
An efficient resource-optimized learning prefetcher for solid state drives. 273-276 - George Ungureanu, José Edil G. de Medeiros, Ingo Sander:
Bridging discrete and continuous time models with atoms. 277-280 - Robert Lajos Bücs, Maximilian Fricke, Rainer Leupers, Gerd Ascheid, Stephan Tobies, Andreas Hoffmann:
OHEX: OS-aware hybridization techniques for accelerating MPSoC full-system simulation. 281-284 - Hsin-I Wu, Chi-Kang Chen, Tsung-Ying Lu, Ren-Song Tsay:
A highly efficient full-system virtual prototype based on virtualization-assisted approach. 285-288 - Mahroo Zandrahimi, Philippe Debaud, Armand Castillejo, Zaid Al-Ars:
Industrial evaluation of transition fault testing for cost effective offline adaptive voltage scaling. 289-292 - Deepak M. Mathew, Martin Schultheis, Carl Christian Rheinländer, Chirag Sudarshan, Christian Weis, Norbert Wehn, Matthias Jung:
An analysis on retention error behavior and power consumption of recent DDR4 DRAMs. 293-296 - Marcello Dalpasso, Davide Bertozzi, Michele Favalli:
A Boolean model for delay fault testing of emerging digital technologies based on ambipolar devices. 297-300 - Rohini Gulve, Virendra Singh:
ATPG power guards: On limiting the test power below threshold. 301-304 - Alexander S. Kulikov:
Improving circuit size upper bounds using SAT-solvers. 305-308 - Mathias Soeken, Winston Haaswijk, Eleonora Testa, Alan Mishchenko, Luca Gaetano Amarù, Robert K. Brayton, Giovanni De Micheli:
Practical exact synthesis. 309-314 - Krishanu Debnath, Rajeev Murgai, Mayank Jain, Janet Olson:
SAT-based redundancy removal. 315-318 - Soheil Hashemi, Hokchhay Tann, Francesco Buttafuoco, Sherief Reda:
Approximate computing for biometrie security systems: A case study on iris scanning. 319-324 - Tai-Chou Wu, Yu-ping Ma, Li-Pin Chang:
Flash read disturb management using adaptive cell bit-density with in-place reprogramming. 325-330 - Ahmad Albaqsami, Maryam S. Hosseini, Nader Bagherzadeh:
HTF-MPR: A heterogeneous TensorFlow mapper targeting performance using genetic algorithms and gradient boosting regressors. 331-336 - Reena Panda, Xinnian Zheng, Andreas Gerstlauer, Lizy Kurian John:
CAMP: Accurate modeling of core and memory locality for proxy generation of big-data applications. 337-342 - Jiajun Li, Guihai Yan, Wenyan Lu, Shuhao Jiang, Shijun Gong, Jingya Wu, Xiaowei Li:
SmartShuttle: Optimizing off-chip memory accesses for deep learning accelerators. 343-348 - Tim Schmidt, Zhongqi Cheng, Rainer Dömer:
Port call path sensitive conflict analysis for instance-aware parallel SystemC simulation. 349-354 - Aatreyi Bal, Sanghamitra Roy, Koushik Chakraborty:
Trident: A comprehensive timing error resilient technique against choke points at NTC. 355-360 - Byung-Su Kim, Joon-Sung Yang:
Bayesian theory based switching probability calculation method of critical timing path for on-chip timing slack monitoring. 361-366 - Venakata Chaitanya Krishna Chekuri, Monodeep Kar, Arvind Singh, Saibal Mukhopadhyay:
Performance based tuning of an inductive integrated voltage regulator driving a digital core against process and passive variations. 367-372 - Sudipta Mondal, Krishnendu Chakrabarty:
Pre-assembly testing of interconnects in embedded multi-die interconnect bridge (EMIB) dies. 373-378 - Felipe A. Kuentzer, Leonardo Rezende Juracy, Alexandre M. Amory:
On the reuse of timing resilient architecture for testing path delay faults in critical paths. 379-384 - Jan Burchard, Dominik Erb, Bernd Becker:
Characterization of possibly detected faults by accurately computing their detection probability. 385-390 - Sanu Mathew, Sudhir Satpathy, Vikram B. Suresh, Ram Krishnamurthy:
Ultra-low energy circuit building blocks for security technologies. 391-394 - Itamar Levi, Yehuda Rudin, Alexander Fish, Osnat Keren:
Embedded randomness and data dependencies design paradigm: Advantages and challenges. 395-400 - Arvind Singh, Monodeep Kar, Sanu Mathew, Anand Rajan, Vivek De, Saibal Mukhopadhyay:
Exploiting on-chip power management for side-channel security. 401-406 - Jilan Lin, Lixue Xia, Zhenhua Zhu, Hanbo Sun, Yi Cai, Hui Gao, Ming Cheng, Xiaoming Chen, Yu Wang, Huazhong Yang:
Rescuing memristor-based computing with non-linear resistance levels. 407-412 - Omid Akbari, Mehdi Kamal, Ali Afzali-Kusha, Massoud Pedram, Muhammad Shafique:
PX-CGRA: Polymorphic approximate coarse-grained reconfigurable architecture. 413-418 - Sam Amiri, Mohammad Hosseinabady, Simon McIntosh-Smith, José L. Núñez-Yáñez:
Multi-precision convolutional neural networks on heterogeneous hardware. 419-424 - Onur Tunali, Mustafa Altun:
Logic synthesis and defect tolerance for memristive crossbar arrays. 425-430 - Alma Pröbstl, Sangyoung Park, Swaminathan Narayanaswamy, Sebastian Steinhorst, Samarjit Chakraborty:
SOH-aware active cell balancing strategy for high power battery packs. 431-436 - Sara Vinco, Lorenzo Bottaccioli, Edoardo Patti, Andrea Acquaviva, Enrico Macii, Massimo Poncino:
GIS-based optimal photovoltaic panel floorplanning for residential installations. 437-442 - Jörg Fickenscher, Jens Schlumberger, Frank Hannig, Jürgen Teich, Mohamed Essayed Bouzouraa:
Cell-based update algorithm for occupancy grid maps and hybrid map for ADAS on embedded GPUs. 443-448 - Bahareh Pourshirazi, Majed Valad Beigi, Zhichun Zhu, Gokhan Memik:
WALL: A writeback-aware LLC management for PCM-based main memory systems. 449-454 - Pedro Benedicte, Carles Hernández, Jaume Abella, Francisco J. Cazorla:
Design and integration of hierarchical-placement multi-level caches for real-time systems. 455-460 - Kyle Kuan, Tosiron Adegbija:
LARS: Logically adaptable retention time STT-RAM cache for embedded systems. 461-466 - Mohd Syafiq Mispan, Haibo Su, Mark Zwolinski, Basel Halak:
Cost-efficient design for modeling attacks resistant PUFs. 467-472 - Orlando Arias, Fahim Rahman, Mark M. Tehranipoor, Yier Jin:
Device attestation: Past, present, and future. 473-478 - Omid Aramoon, Xi Chen, Gang Qu:
A reconfigurable scan network based IC identification for embedded devices. 479-484 - Lai Leng Woo, Mark Zwolinski, Basel Halak:
Early detection of system-level anomalous behaviour using hardware performance counters. 485-490 - Leilai Shao, Tsung-Ching Huang, Ting Lei, Zhenan Bao, Raymond G. Beausoleil, Kwang-Ting Cheng:
Compact modeling of carbon nanotube thin film transistors for flexible circuit design. 491-496 - Benjamin J. Fletcher, Shidhartha Das, Terrence S. T. Mak:
A high-speed design methodology for inductive coupling links in 3D-ICs. 497-502 - Marcel Walter, Robert Wille, Daniel Große, Frank Sill Torres, Rolf Drechsler:
An exact method for design exploration of quantum-dot cellular automata. 503-508 - Soheil Nazar Shahsavani, Bo Zhang, Massoud Pedram:
Accurate margin calculation for single flux quantum logic cells. 509-514 - Yue Ma, Thidapat Chantem, Robert P. Dick, Xiaobo Sharon Hu:
Improving reliability for real-time systems through dynamic recovery. 515-520 - Johannes Bund, Christoph Lenzen, Moti Medina:
Optimal metastability-containing sorting networks. 521-526 - Kai-Chiang Wu, Tien-Hung Tseng, Shou-Chun Li:
MAUI: Making aging useful, intentionally. 527-532 - Hwisoo So, Moslem Didehban, Yohan Ko, Aviral Shrivastava, Kyoungwoo Lee:
EXPERT: Effective and flexible error protection by redundant multithreading. 533-538 - Björn Forsberg, Luca Benini, Andrea Marongiu:
HePREM: Enabling predictable GPU execution on heterogeneous SoC. 539-544 - Ilaria Scarabottolo, Giovanni Ansaloni, Laura Pozzi:
Circuit carving: A methodology for the design of approximate hardware. 545-550 - Katayoun Neshatpour, Farnaz Behnia, Houman Homayoun, Avesta Sasan:
ICNN: An iterative implementation of convolutional neural networks to enable energy and computational complexity aware dynamic approximation. 551-556 - Anuj Pathania, Jörg Henkel:
Task scheduling for many-cores with S-NUCA caches. 557-562 - Sung-Ming Wu, Kai-Hsiang Lin, Li-Pin Chang:
KVSSD: Close integration of LSM trees and flash translation layer for write-efficient KV store. 563-568 - Pu Pang, Yixun Zhang, Tianjian Li, Sung Kyu Lim, Quan Chen, Xiaoyao Liang, Li Jiang:
In-growth test for monolithic 3D integrated SRAM. 569-572 - Jeroen P. G. van Dijk, Andrei Vladimirescu, Masoud Babaie, Edoardo Charbon, Fabio Sebastiano:
A co-design methodology for scalable quantum processors and their classical electronic interface. 573-576 - Sina Boroumand, Hadi Parandeh-Afshar, Philip Brisk:
Approximate quaternary addition with the fast carry chains of FPGAs. 577-580 - Seongmin Hong, Inho Lee, Yongjun Park:
NN compactor: Minimizing memory and logic resources for small neural networks. 581-584 - Alexander Lamprecht, Swaminathan Narayanaswamy, Sebastian Steinhorst:
Improving fast charging efficiency of reconfigurable battery packs. 585-588 - Arun Adiththan, S. Ramesh, Soheil Samii:
Cloud-assisted control of ground vehicles using adaptive computation offloading techniques. 589-592 - Evangelos Vasilakis, Vassilis Papaefstathiou, Pedro Trancoso, Ioannis Sourdis:
FusionCache: Using LLC tags for DRAM cache. 593-596 - Philipp Niemann, Robert Wille, Rolf Drechsler:
Improved synthesis of Clifford+T quantum functionality. 597-600 - Yuyang Wang, M. Ashkan Seyedi, Rui Wu, Jared Hulme, Marco Fiorentino, Raymond G. Beausoleil, Kwang-Ting Cheng:
Energy-efficient channel alignment of DWDM silicon photonic transceivers. 601-604 - Shubham Rai, Ansh Rupani, Dennis Walter, Michael Raitza, Andre Heinzig, Tim Baldauf, Jens Trommer, Christian Mayr, Walter M. Weber, Akash Kumar:
A physical synthesis flow for early technology evaluation of silicon nanowire based reconfigurable FETs. 605-608 - Daniel Mueller-Gritschneder, Martin Dittrich, Josef Weinzierl, Eric Cheng, Subhasish Mitra, Ulf Schlichtmann:
ETISS-ML: A multi-level instruction set simulator with RTL-level fault injection support for the evaluation of cross-layer resiliency techniques. 609-612 - Rafael Billig Tonetto, Gabriel L. Nazar, Antonio Carlos Schneider Beck:
Precise evaluation of the fault sensitivity of OoO superscalar processors. 613-616 - Hyukjoong Kim, Kyuhwa Han, Dongkun Shin:
StreamFTL: Stream-level address translation scheme for memory constrained flash storage. 617-620 - Basireddy Karunakar Reddy, Geoff V. Merrett, Bashir M. Al-Hashimi, Amit Kumar Singh:
Online concurrent workload classification for multi-core energy management. 621-624