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Nidhi Agrawal
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2020 – today
- 2022
- [c7]Vijayakumar Thangamariappan, Nidhi Agrawal, Jason Kim, Constantinos Xanthopoulos, Ken Butler, Ira Leventhal, Joe Xiao:
Improvements in Automated IC Socket Pin Defect Detection. ITC 2022: 568-572 - 2020
- [c6]Nidhi Agrawal, Min-Jian Yang, Constantinos Xanthopoulos, Vijayakumar Thangamariappan, Joe Xiao, Chee-Wah Ho, Keith Schaub, Ira Leventhal:
Automated Socket Anomaly Detection through Deep Learning. ITC 2020: 1-5
2010 – 2019
- 2016
- [j3]Vlad V. Simianu, Margaret A. Grounds, Susan L. Joslyn, Jared E. LeClerc, Anne P. Ehlers, Nidhi Agrawal, Rafael Alfonso-Cristancho, Abraham D. Flaxman, David R. Flum:
Understanding clinical and non-clinical decisions under uncertainty: a scenario-based survey. BMC Medical Informatics Decis. Mak. 16: 153:1-153:9 (2016) - 2013
- [c5]Om Prakash Thakur
, Nidhi Agrawal:
Error in mathematical modelling and enhancement of sensing performance of electrostrictive capacitive sensors. ICST 2013: 430-433
1990 – 1999
- 1999
- [j2]C. P. Ravikumar, Gurjeet S. Saund, Nidhi Agrawal:
A functional-level testability measure for register-level circuits and its estimation. Microprocess. Microsystems 22(9): 535-542 (1999) - 1998
- [c4]Nidhi Agrawal, C. P. Ravikumar:
Adaptive Routing Based on Deadlock Recovery. Euro-Par 1998: 981-988 - 1997
- [c3]Nidhi Agrawal, C. P. Ravikumar:
An Euler Path Based Technique for Deadlock-free Multicasting. ICPP 1997: 378-384 - 1996
- [j1]Nidhi Agrawal, C. P. Ravikumar:
Fault-tolerant routing in multiply twisted cube topology. J. Syst. Archit. 42(4): 279-288 (1996) - [c2]Nidhi Agrawal, Parul Agarwal, C. P. Ravikumar:
Efficient Delay Test Generation for Modular Circuits. Great Lakes Symposium on VLSI 1996: 220- - 1995
- [c1]C. P. Ravikumar, Gurjeet S. Saund, Nidhi Agrawal:
A STAFAN-like functional testability measure for register-level circuits. Asian Test Symposium 1995: 192-198
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