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ORCIDJörg Berthold
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2010 – 2019
- 2016
[j6]Christian Schlünder, Jörg Berthold, Fabian Proebster, Andreas Martin, Wolfgang Gustin, Hans Reisinger:
Degradation and recovery of variability due to BTI. Microelectron. Reliab. 64: 179-184 (2016)- 2011
- [c15]Ulrich Ramacher, Wolfgang Raab, J. A. Ulrich Hachmann, Dominik Langen, Jörg Berthold, R. Kramer, A. Schackow, Cyprian Grassmann, Mirko Sauermann, P. Szreder, F. Capar, G. Obradovic, W. Xu, Nico Brüls, Kang Lee, Eugene Weber, Ray Kuhn, John Harrington:
Architecture and implementation of a Software-Defined Radio baseband processor. ISCAS 2011: 2193-2196 - 2010
- [c14]Wolfgang Raab, Jörg Berthold, J. A. Ulrich Hachmann, Dominik Langen, Michael Schreiner, Holger Eisenreich, Jens-Uwe Schluessler, Georg Ellguth:
Low power design of the X-GOLD® SDR 20 baseband processor. DATE 2010: 792-793
2000 – 2009
- 2007
- [j5]Thomas Lüftner, Jörg Berthold, Christian Pacha, Georg Georgakos, Guillaume Sauzon, Olaf Hömke, Jurij Beshenar, Peter Mahrla, Knut M. Just, Peter Hober, Stephan Henzler, Doris Schmitt-Landsiedel, Andre Yakovleff, Axel Klein, Richard J. Knight, Pramod Acharya, Andre Bonnardot, Steffen Buch, Matthias Sauer:
A 90-nm CMOS Low-Power GSM/EDGE Multimedia-Enhanced Baseband Processor With 380-MHz ARM926 Core and Mixed-Signal Extensions. IEEE J. Solid State Circuits 42(1): 134-144 (2007) - [j4]Matthias Eireiner, Stephan Henzler, Georg Georgakos, Jörg Berthold, Doris Schmitt-Landsiedel:
In-Situ Delay Characterization and Local Supply Voltage Adjustment for Compensation of Local Parametric Variations. IEEE J. Solid State Circuits 42(7): 1583-1592 (2007) - [c13]Christian Pacha, Klaus von Arnim, Florian Bauer, Thomas Schulz, Wade Xiong, K. T. San, Andrew Marshall, Thomas Baumann, C. Rinn Cleavelin, Klaus Schruefer, Jörg Berthold:
Efficiency of low-power design techniques in Multi-Gate FET CMOS Circuits. ESSCIRC 2007: 111-114 - [c12]Thomas Baumann, Jörg Berthold, T. Niedermeier, Tim Schoenauer, J. Dienstuhl, Doris Schmitt-Landsiedel, Christian Pacha:
Performance improvement of embedded low-power microprocessor cores by selective flip flop replacement. ESSCIRC 2007: 308-311 - 2006
- [j3]Stephan Henzler, Georg Georgakos, Matthias Eireiner, Thomas Nirschl, Christian Pacha, Jörg Berthold, Doris Schmitt-Landsiedel:
Dynamic state-retention flip-flop for fine-grained power gating with small design and power overhead. IEEE J. Solid State Circuits 41(7): 1654-1661 (2006) - [c11]Thomas Lüftner, Jörg Berthold, Christian Pacha, Georg Georgakos, Guillaume Sauzon, Olaf Hömke, Jurij Beshenar, Peter Mahrla, Knut M. Just, Peter Hober, Stephan Henzler, Doris Schmitt-Landsiedel, Andre Yakovleff, Axel Klein, Richard J. Knight, Pramod Acharya, Hamid Mabrouki, Goulhamid Juhoor, Matthias Sauer:
A 90nm CMOS low-power GSM/EDGE multimedia-enhanced baseband processor with 380MHz ARM9 and mixed-signal extensions. ISSCC 2006: 952-961 - [c10]Christian Pacha, Klaus von Arnim, Thomas Schulz, Weize Xiong, Michael Gostkowski, Gerhard Knoblinger, Andrew Marshall, Thomas Nirschl, Jörg Berthold, Christian Russ, Harald Gossner, Charvaka Duvvury, Paul Patruno, C. Rinn Cleavelin, Klaus Schruefer:
Circuit design issues in multi-gate FET CMOS technologies. ISSCC 2006: 1656-1665 - 2005
- [j2]Klaus von Arnim, Eduardo Borinski, Peter Seegebrecht, Horst Fiedler, Ralf Brederlow
, Roland Thewes, Jörg Berthold, Christian Pacha:
Efficiency of body biasing in 90-nm CMOS for low-power digital circuits. IEEE J. Solid State Circuits 40(7): 1549-1556 (2005) - [c9]Stephan Henzler, Thomas Nirschi, Christian Pacha, Peter Spindler, Philip Teichmann, Michael Fulde, Jürgen Fischer, Matthias Eireiner, Thomas Fischer, Georg Georgakos, Jörg Berthold, Doris Schmitt-Landsiedel:
Dynamic state-retention flip flop for fine-grained sleep-transistor scheme. ESSCIRC 2005: 145-148 - 2004
- [c8]Klaus von Arnim, Eduardo Borinski, Peter Seegebrecht, Horst Fiedler, Ralf Brederlow, Roland Thewes, Jörg Berthold, Christian Pacha:
Efficiency of body biasing in 90 nm CMOS for low power digital circuits. ESSCIRC 2004: 175-178 - [c7]Stephan Henzler, Georg Georgakos, Jörg Berthold, Doris Schmitt-Landsiedel:
Single Supply Voltage High-Speed Semi-dynamic Level-Converting Flip-Flop with Low Power and Area Consumption. PATMOS 2004: 392-401 - [c6]Stephan Henzler, Georg Georgakos, Jörg Berthold, Doris Schmitt-Landsiedel:
Two Level Compact Simulation Methodology for Timing Analysis of Power-Switched Circuits. PATMOS 2004: 789-798 - 2003
- [c5]Ettore Amirante, Jürgen Fischer, Markus Lang, Agnese Bargagli-Stoffi, Jörg Berthold, Christoph Heer, Doris Schmitt-Landsiedel:
An ultra low-power adiabatic adder embedded in a standard 0.13μm CMOS environment. ESSCIRC 2003: 599-602 - [c4]Tim Schoenauer, Jörg Berthold, Christoph Heer:
Reduced Leverage of Dual Supply voltages in Ultra Deep Submicron Technologies. PATMOS 2003: 41-50 - [c3]Stephan Henzler, Philip Teichmann, Markus Koban, Jörg Berthold, Georg Georgakos, Doris Schmitt-Landsiedel:
Impact of Gate Leakage on Efficiency of Circuit Block Switch-Off Schemes. VLSI-SoC (Selected Papers) 2003: 229-245 - [c2]Stephan Henzler, Markus Koban, Doris Schmitt-Landsiedel, Jörg Berthold, Georg Georgakos:
Design Aspects and Technological Scaling Limits of ZigZag Circuit Block Switch-Off Schemes. VLSI-SOC 2003: 246-251
1990 – 1999
- 1997
- [j1]M. Eisele, Jörg Berthold, Doris Schmitt-Landsiedel, R. Mahnkopf:
The impact of intra-die device parameter variations on path delays and on the design for yield of low voltage digital circuits. IEEE Trans. Very Large Scale Integr. Syst. 5(4): 360-368 (1997) - 1996
- [c1]M. Eisele, Jörg Berthold, Doris Schmitt-Landsiedel, R. Mahnkopf:
The impact of intra-die device parameter variations on path delays and on the design for yield of low voltage digital circuits. ISLPED 1996: 237-242
Coauthor Index
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