default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDESSCIRC 2007: Munich, Germany
- Doris Schmitt-Landsiedel, Tobias Noll:
33rd European Solid-State Circuits Conference, ESSCIRC 2007, Munich, Germany, 11-13 September 2007. IEEE 2007, ISBN 978-1-4244-1125-2 - Wolfgang Ziebart:
Technical and economical trends in microelectronics. 1-10 - André DeHon:
Architecture approaching the atomic scale. 11-20 - Albert Theuwissen:
CMOS image sensors: State-of-the-art and future perspectives. 21-27 - Sani R. Nassif:
Model to Hardware matching for nano-meter scale technologies. 28-31 - Kazunari Ishimaru
:
45nm/32nm CMOS ˜ Challenge and Perspective ˜. 32-35 - Peter Fromherz:
Joining microelectronics and microionics: Nerve cells and brain tissue on semiconductor chips. 36-45 - Dago M. De Leeuw:
Large-area molecular junctions. 46 - Kinam Kim, Donggun Park:
The future outlook of memory devices. 47 - Enrico Sangiorgi, Pierpaolo Palestri, David Esseni, Claudio Fiegna, Luca Selmi:
The Monte Carlo approach to transport modeling in deca-nanometer MOSFETs. 48-57 - Peter R. Kinget:
Designing analog and RF circuits for ultra-low supply voltages. 58-67 - Kiyoo Itoh, Masashi Horiguchi, Masanao Yamaoka:
Low-voltage limitations of memory-rich nano-scale CMOS LSIs. 68-75 - Kofi A. A. Makinwa, Michiel A. P. Pertijs, Jeroen C. v. d. Meer, Johan H. Huijsing:
Smart sensor design: The art of compensation and cancellation. 76-82 - Andrew B. Kahng:
Key directions and a roadmap for electrical design for manufacturability. 83-88 - Wei Zhao, Yu Cao, Frank Liu, Kanak Agarwal, Dhruva Acharyya, Sani R. Nassif, Kevin J. Nowka:
Rigorous extraction of process variations for 65nm CMOS design. 89-92 - Binjie Cheng, Scott Roy, A. Asenov:
The scalability of 8T-SRAM cells under the influence of intrinsic parameter fluctuations. 93-96 - Bedrich J. Hosticka:
Analog circuits for sensors. 97-102 - Christian Koch, Jürgen Oehm, Jannik Emde, Wolfram Budde:
Integrated sensor for light source position measurement applicable in SOI technology. 103-106 - Nitz Saputra, Mina Danesh, Alessandro Baiano, Ryoichi Ishihara, John R. Long, Wim Metselaar, C. I. M. Beenakker, Nobuo Karaki, Y. Hiroshima, Satoshi Inoue:
Single-grain Si thin-film transistors for analog and RF circuit applications. 107-110 - Christian Pacha, Klaus von Arnim, Florian Bauer, Thomas Schulz, Wade Xiong, K. T. San, Andrew Marshall, Thomas Baumann, C. Rinn Cleavelin, Klaus Schruefer, Jörg Berthold:
Efficiency of low-power design techniques in Multi-Gate FET CMOS Circuits. 111-114 - Toshiki Kanamoto, Yasuhiro Ogasahara, Keiko Natsume, Kenji Yamaguchi, Hiroyuki Amishiro, Tetsuya Watanabe, Masanori Hashimoto:
Impact of well edge proximity effect on timing. 115-118 - Sushant Suryagandh, Mayank Gupta, Zhiyuan Wu, Srinath Krishnan, Mario Pelella, Jung-Suk Goo, Ciby Thuruthiyil, Judy X. An, Brian Q. Chen, Niraj Subba, Luis Zamudio, James Yonemura, Ali B. Icel:
Impact of stress on various circuit characteristics in 65nm PDSOI technology. 119-122 - Michael Fulde, Abdelkarim Mercha, Cedric Gustin, Bertrand Parvais, Vaidyanathan Subramanian, Klaus von Arnim, Florian Bauer, Klaus Schruefer, Doris Schmitt-Landsiedel, Gerhard Knoblinger:
Analog design challenges and trade-offs using emerging materials and devices. 123-126 - Alan Chi Wai Wong, Ganesh Kathiresan, Chung Kei Thomas Chan, Omar El-Jamaly, Alison J. Burdett:
A 1V wireless transceiver for an ultra low power SoC for biotelemetry applications. 127-130 - Muhammad Anis, Reinhard Tielert:
Low power UWB pulse radio transceiver front-end. 131-134 - Davide Guermandi, Simone Gambini, Jan M. Rabaey:
A 1 V 250 KPPS 90 NM CMOS pulse based transceiver for CM-range wireless communication. 135-138 - Alessio Vallese, Andrea Bevilacqua, Christoph Sandner, Marc Tiebout, Andrea Gerosa, Andrea Neviani:
An analog front-end with integrated notch filter for 3-5 GHz UWB receivers in 0.13 μm CMOS. 139-142 - Chao-Shiun Wang, Juin-Wei Huang, Shon-Hang Wen, Shih-Huang Yeh, Chorng-Kuang Wang:
A CMOS RF front-end with on-chip antenna for V-band broadband wireless communications. 143-146 - Imran Ahmed, David A. Johns:
An 11-bit 45MS/s pipelined ADC with rapid calibration of DAC errors in a multi-bit pipeline stage. 147-150 - Cheng-Chung Hsu, Chen-Chih Huang, Ying-Hsi Lin, Chao-Cheng Lee:
A 10b 200MS/s pipelined folding ADC with offset calibration. 151-154 - Yihui Chen, Qiuting Huang, Thomas Burger:
A 1.2V 200-MS/s 10-bit folding and interpolating ADC in 0.13-μm CMOS. 155-158 - Imran Ahmed, David A. Johns:
A high bandwidth power scaleable sub-sampling 10-bit pipelined ADC with embedded sample and hold. 159-162 - Tatsuo Nakagawa, Tatsuji Matsuura, Eiki Imaizumi, Junya Kudoh, Goichi Ono, Masayuki Miyazaki, Akira Maeki, Yuji Ogata, Shinsuke Kobayashi, Noboru Koshizuka, Ken Sakamura:
1-GHz Input bandwidth 6-bit under-sampling A/D converter for UWB-IR receiver. 163-166 - Mario Manninger:
Power management for portable devices. 167-173 - Hong-Wei Huang, Chun-Yu Hsieh, Ke-Horng Chen, Sy-Yen Kuo:
Adaptive frequency control technique for enhancing transient performance of DC-DC converters. 174-177 - Kiyokazu Umimura, Hiroki Sakurai, Yasuhiro Sugimoto:
A CMOS Current-mode DC-DC converter with input and output voltage-independent stability and frequency characteristics utilizing a quadratic slope compensation scheme. 178-181 - Mikkel Hoyerby, Michael A. E. Andersen, Pietro Andreani:
A 0.35μm 50V CMOS sliding-mode control IC for buck converters. 182-185 - Hyunsoo Chae, Sangdon Jung, Chulwoo Kim:
A wide-range duty-independent all-digital multiphase clock generator. 186-189 - David Levacq, Muhammad Yazid, Hiroshi Kawaguchi, Makoto Takamiya, Takayasu Sakurai:
Half VDD Clock-Swing Flip-Flop with Reduced Contention for up to 60% Power Saving in Clock Distribution. 190-193 - Stephan Henzler, Siegmar Koeppe, Dominik Lorenz, Winfried Kamp, Ronald Kuenemund, Doris Schmitt-Landsiedel:
Variation tolerant high resolution and low latency time-to-digital converter. 194-197 - Shanthi Pavan, Nagendra Krishnapura, Ramalingam Pandarinathan, Prabu Sankar:
A 90μW 15-bit ΔΣ ADC for digital audio. 198-201 - Simone Gambini, Jan M. Rabaey:
A 100KS/s 65dB DR Σ - Δ ADC with 0.65V supply voltage. 202-205 - Ulrik Wismar, Dag T. Wisland, Pietro Andreani:
A 0.2V, 7.5 μW, 20 kHz ΣΔ modulator with 69 dB SNR in 90 nm CMOS. 206-209 - Tien-Yu Lo, Chung-Chih Hung, Mohammed Ismail:
A wide tuning range Gm-C filter for multi-mode direct-conversion wireless receivers. 210-213 - Aránzazu Otín, Santiago Celma, Concepción Aldea:
A 40-200 MHz programmable 4th-order Gm-C filter with auto-tuning system. 214-217 - Stephane Razafimandimby, Cyrille Tilhac, Andreia Cathelin, Andreas Kaiser, Didier Belot:
Digital tuning of an analog tunable bandpass BAW-filter at GHz frequency. 218-221 - John V. McCanny, Sakir Sezer, Máire O'Neill:
Exploring technology related design-space limitations of high performance network processing. 222-231 - Byeong-Gyu Nam, Hoi-Jun Yoo:
A low-power vector processor using logarithmic arithmetic for handheld 3d graphics systems. 232-235 - Marian Verhelst, Wim Dehaene:
A flexible, ultra-low power 35pJ/pulse digital back-end for a QAC UWB receiver. 236-239 - Martin Anderson, Lars Sundström:
A 312-MHz CT Δ∑ modulator using a SC feedback DAC with reduced peak current. 240-243 - Olujide A. Adeniran, Andreas Demosthenous:
A 14-mW, 153.6-MHz clock-rate Δ∑ modulator for WCDMA with 77-dB SFDR using constant resistance CMOS input sampling switch. 244-247 - Ivano Galdi, Edoardo Bonizzoni, Franco Maloberti, Gabriele Manganaro, Piero Malcovati:
Two-path band-pass Δ∑ modulator with 40-MHz IF 72-dB DR at 1-MHz bandwidth consuming 16 mW. 248-251 - YuQing Yang, Terry Sculley, Jacob Abraham:
A single die 124dB stereo audio delta sigma ADC with 111dB THD. 252-255 - Michael Wendt, Lenz Thoma, Bernhard Wicht, Doris Schmitt-Landsiedel:
A configurable High-Side/ low-Side Driver. 256-259 - Day-Uei Li, Hsin-Chao Chen:
10Gb/s 0.13µm CMOS laser drivers with extinction ratio control using thermistors. 260-263 - Junfeng Zhou, Wim Dehaene:
A fully integrated low EMI noise power supply technique for CMOS digital IC's in automotive applications. 264-267 - Mike Wens, Koen Cornelissens, Michiel Steyaert:
A fully-integrated 0.18µm CMOS DC-DC step-up converter, using a bondwire spiral inductor. 268-271 - Patrick Reynaert, Ali M. Niknejad:
Power combining techniques for RF and mm-wave CMOS power amplifiers. 272-275 - Yanyu Jin, Mihai A. T. Sanduleanu, Eduardo Alarcon Rivero, John R. Long:
A millimeter-wave power amplifier with 25dB power gain and +8dBm saturated output power. 276-279 - Mikko Varonen, Mikko Kärkkäinen, Kari A. I. Halonen:
Millimeter-wave amplifiers in 65-nm CMOS. 280-283 - Sascha Thoss, Olaf Machul, Bedrich J. Hosticka:
A novel architecture for inductive proximity sensors using sigma delta modulation. 284-287 - Qiang Li, Kuo Hwi Tan, Tee Hui Teo, Rajinder Singh:
A I-V 36-pW low-noise adaptive interface IC for portable biomedical applications. 288-291 - Cheng Zhang, Kofi A. A. Makinwa:
Interface electronics for a CMOS electrothermal frequency-locked-loop. 292-295 - Inge Diehl, Karsten Hansen, Christian Reckleben:
A mixed-signal readout chip for a 7-cell Si-Drift detector in 0.35-μm BiCMOS technology. 296-299 - Alexandre Valentian, Edith Beigné:
Gate bias circuit for an SCCMOS power switch achieving maximum leakage reduction. 300-303 - Armin Tajalli, Eric A. Vittoz, Yusuf Leblebici, Elizabeth J. Brauer:
Ultra low power subthreshold MOS current mode logic circuits using a novel load device concept. 304-307 - Thomas Baumann, Jörg Berthold, T. Niedermeier, Tim Schoenauer, J. Dienstuhl, Doris Schmitt-Landsiedel, Christian Pacha:
Performance improvement of embedded low-power microprocessor cores by selective flip flop replacement. 308-311 - Hui Shao, Chi-Ying Tsui:
A robust, input voltage adaptive and low energy consumption level converter for sub-threshold logic. 312-315 - Amit Agarwal, Nilanjan Banerjee, Steven K. Hsu, Ram K. Krishnamurthy, Kaushik Roy:
A 200mV to 1.2V, 4.4MHz to 6.3GHz, 48×42b 1R/1W programmable register file in 65nm CMOS. 316-319 - Koh Johguchi, Yuya Mukuda, Shinya Izumi, Hans Jürgen Mattausch, Tetsushi Koide:
A 0.6-Tbps, 16-port SRAM design with 2-stage- pipeline and multi-stage-sensing scheme. 320-323 - Joo-Young Kim, Donghyun Kim, Seungjin Lee, Kwanho Kim, Seonghyun Jeon, Hoi-Jun Yoo:
Visual image processing RAM for fast 2-D data location search. 324-327 - Alexander Flocke, Tobias G. Noll:
Fundamental analysis of resistive nano-crossbars for the use in hybrid Nano/CMOS-memory. 328-331 - Estelle Labonne, Gilles Sicard, Marc Renaudin:
An on-pixel FPN reduction method for a high dynamic range CMO S imager. 332-335 - Noriko Ide, Woonghee Lee, Nana Akahane, Shigetoshi Sugawa:
A Wide DR and linear response CMOS image sensor with three photocurrent integrations in photodiodes, lateral overflow capacitors and column capacitors. 336-339 - Daniel Durini, Werner Brockherde, Bedrich J. Hosticka:
MOS-Capacitor based CMOS time-compression photogate pixel for time-of-flight imaging. 340-343 - G. Reza Chaji, Arokia Nathan:
A Sub-μA fast-settling current-programmed pixel circuit for AMOLED displays. 344-347 - Baudouin Martineau, Andreia Cathelin, François Danneville, Andreas Kaiser, Gilles Dambrine, Sylvie Lépilliet, Frederic Gianesello, Didier Belot:
80 GHz low noise amplifiers in 65nm CMOS SOI. 348-351 - Stefano Pellerano, Yorgos Palaskas, Krishnamurthy Soumyanath:
A 64GHz 6.5 dB NF 15.5 dB gain LNA in 90nm CMOS. 352-355 - Saverio Trotta, Bernhard Dehlink, Herbert Knapp, Klaus Aufinger, Thomas F. Meister, Josef Böck, Werner Simbürger, Arpad L. Scholtz:
Design considerations for low-noise, highly-linear millimeter-wave mixers in SiGe bipolar technology. 356-359 - Mikko Varonen, Mikko Kärkkäinen, Kari A. I. Halonen:
V-band balanced resistive mixer in 65-nm CMOS. 360-363 - Stephan C. Blaakmeer, Eric A. M. Klumperink, Bram Nauta, Domine M. W. Leenaerts:
An inductorless wideband balun-LNA in 65nm CMOS with balanced output. 364-367 - Lorenzo Tripodi, Hans Brekelmans:
Low-noise variable-gain amplifier in 90-nm CMOS for TV on mobile. 368-371 - Bevin G. Perumana, Jing-Hong Conan Zhan, Stewart S. Taylor, Joy Laskar:
A 5 GHz, 21 dBm output-IP3 resistive feedback LNA in 90-nm CMOS. 372-375 - Jonathan Borremans, Piet Wambacq, Geert Van der Plas, Yves Rolain, Maarten Kuijk:
A switchable low-area 2.4-and-5 GHz dual-band LNA in digital CMOS. 376-379 - Willem Laflere, Michiel Steyaert, Jan Craninckx:
A power amplifier driver using self-oscillating pulse-width modulators. 380-383 - Wim Dehaene, Stefan Cosemans, Anselme Vignon, F. Catthoora, Peter Geens:
Embedded SRAM design in deep deep submicron technologies. 384-391 - Florian Bauer, Klaus von Arnim, Christian Pacha, Thomas Schulz, Michael Fulde, Axel Nackaerts, M. Jurczak, Wade Xiong, K. T. San, C. Rinn Cleavelin, Klaus Schruefer, Georg Georgakos, Doris Schmitt-Landsiedel:
Layout options for stability tuning of SRAM cells in multi-gate-FET technologies. 392-395 - Masanao Yamaoka, Takayuki Kawahara:
Operating-margin-improved SRAM with column-at-a-time body-bias control technique. 396-399 - Jiajing Wang, Amith Singhee, Rob A. Rutenbar, Benton H. Calhoun:
Statistical modeling for the minimum standby supply voltage of a full SRAM array. 400-403 - Ali Heidary, Gerard C. M. Meijer:
An integrated switched-capacitor front-end for capacitive sensors with a wide dynamic range. 404-407 - Bernhard Goll, Horst Zimmermann:
A clocked, regenerative comparator in 0.12μm CMOS with tunable sensitivity. 408-411 - L. Lincoln, K. Leung, Howard C. Luong:
A 7-μW clock generator in 0.18-μm CMOS for passive UHF RFID EPC G2 tags. 412-415 - Tsz Fai Kwok, Wing-Hung Ki:
A stable compensation scheme for low dropout regulator in the absence of ESR. 416-419 - Jean-Michel Redoute, Cedric Walravens, Steven Van Winckel, Michiel Steyaert:
An integrated DC current regulator with high EMI suppression. 420-423 - Kostis Vavelidis, Iason Vassiliou, Nikos Haralabidis, Aris Kyranas, Yiannis Kokolakis, Stamatis Bouras, George Kamoulakos, Charalampos Kapnistis, Spyros Kavadias, Nikos Kanakaris, Emmanouil Metaxakis, Christos Kokozidis, Hamed Peyravi:
A 65nm CMOS multi-standard, multi-band mobile TV tuner. 424-427 - Sung-Gi Yang, Ji-Ho Ryu, Byoungjoong Kang, Heeseon Shin, Jinhyuck Yu, Sangsoo Ko, Won Ko, Dong-Jin Keum, Woo-Seung Choo, Byeong-Ha Park:
A single-chip CDMA-2000 zero-IF transceiver for band-class 4 with GPS support. 428-431 - Olivier Charlon, S. Clamagirand, V. Vathulya, C. Hritz, Bassem Fahs, O. Burg, C. Caumont, Philippe Barre, L. Guiraud, E. Chartier, V. Blanchard, Helen Waite, William Redman-White, R. Perkins, D. Brunel, E. Soudee:
A dual-mode zero-IF receiver for dual-band CDMA cellular and GPS. 432-435 - Mark Ingels, Charlotte Soens, Jan Craninckx, Vito Giannini, T. Kim, Björn Debaillie, Michael Libois, Michaël Goffioul, Joris Van Driessche:
A CMOS 100 MHz to 6 GHz software defined radio analog front-end with integrated pre-power amplifier. 436-439 - Stefano D'Amico, Marcello De Matteis, Andrea Baschirotto, Nicola Ghittori, Andrea Vigna, Piero Malcovati:
A 5nV/√Hz-IRN, 78dB-gain-range, 78dB-DR multi-standard baseband chain for Bluetooth, UMTS and WLAN. 440-443 - Marco Berkhout:
Clock jitter in class-D audio power amplifiers. 444-447 - Philip Golden, Peter Mole, Barry Harvey:
A +100dB gain, rail-to-rail output, low distortion, low noise amplifier in BiCMOS technology. 448-451 - Philipp Meier auf der Heide, Carsten Bronskowski, Jakob M. Tomasik, Dietmar Schroeder:
A CMOS Operational Amplifier with Constant 68° phase margin over its whole range of noise-power trade-off programmability. 452-455 - Tommaso Borghi, Andrea Bonfanti, Guido Zambra, Riccardo Gusmeroli, Andrea L. Lacaita, Alessandro S. Spinelli, Gytis Baranauskas:
An integrated low-noise multichannel system for neural signals amplification. 456-459 - Xiao Liu, Andreas Demosthenous:
A fail-safe ASIC for implantable neural stimulation. 460-463 - Andreia Cathelin, Baudouin Martineau, N. Seller, S. Douyere, Jean Gorisse, Sébastien Pruvost, Christine Raynaud, Frederic Gianesello, Sébastien Montusclat, Sorin P. Voinigescu, Ali M. Niknejad, Didier Belot, Jean-Pierre Schoellkopf:
Design for millimeter-wave applications in silicon technologies. 464-471 - Hiroaki Hoshino, Ryoichi Tachibana, Toshiya Mitomo, Naoko Ono, Yoshiaki Yoshihara, Ryuichi Fujimoto:
A 60-GHz phase-locked loop with inductor-less prescaler in 90-nm CMOS. 472-475 - Christian Muenker, Robert Weigel:
Spectral PLL built-in self-test for integrated cellular transceivers. 476-479 - Andrea Bonfanti, Carlo Samori, Andrea L. Lacaita:
A multistandard Σ-Δ fractional-N frequency synthesizer for 802.11a/b/g WLAN. 480-483 - Vincent De Heyn, Geert Van der Plas, Julien Ryckaert, Jan Craninckx:
A fast start-up 3GHz-10GHz digitally controlled oscillator for UWB impulse radio in 90nm CMOS. 484-487 - Yao-Hong Liu, Tsung-Hsien Lin:
An energy-efficient 1.5-Mbps wireless FSK transmitter with A ∑Δ-modulated phase rotator. 488-491 - Jérémie Chabloz, David Ruffieux, Alexandre Vouilloz, Paola Tortori, Franz Pengg, Claude Müller, Christian C. Enz:
Frequency synthesis for a low-power 2.4 GHz receiver using a BAW oscillator and a relaxation oscillator. 492-495 - Shouhei Kousai, Mototsugu Hamada, Rui Ito, Tetsuro Itakura:
A novel quality factor tuning scheme for active-RC filters. 496-499 - YoungGun Pu, Sung-Kyu Jung, DoJin Park, JinKyung Kim, Ji-Hoon Jung, Chul Nam, Kang-Yoon Lee:
A CMOS baseband complex bandpass filter with a new Automatic tuning method for PHS applications. 500-503 - Marcello De Matteis, Stefano D'Amico, Vito Giannini, Andrea Baschirotto:
A 550mV 8dBm IIP3 4pth order analog base band filter for WLAN receivers. 504-507 - Lijun Li, Michael M. Green:
An 11.75-Gb/s combined decision feedback equalizer and clock data recovery circuit in 0.18-μm CMOS. 508-511 - Soumya Chandramouli, Franklin Bien, Hyoungsoo Kim, Edward Gebara, Joy Laskar:
A 10-Gb/sec unclocked current-mode logic (CML) analog decision-feedback equalizer (ADFE) in 0.18-μm CMOS. 512-515 - Yong-Hun Oh, Ho-Yong Kang, Kyoohyun Lim, Jongsik Kim, Sang-Gug Lee:
A fully integrated CMOS burst-mode upstream transmitter for gigabit-class passive optical network applications. 516-519 - Olivier Mazouffre, B. Goumballa, Michel Pignol, Claude Neveu, Yann Deval, Jean-Baptiste Bégueret:
A 10-Gb/s CMOS fully integrated ILO-based CDR. 520-523 - M. Kumarasamy Raja, Dan Lei Yan, Aruna B. Ajjikuttira:
A 1.4-psec Jitter 2.5-Gb/s CDR with wide acquisition range in 0.18-μm CMOS. 524-527 - Sitt Tontisirin, Reinhard Tielert:
Gb/s CDR circuit for large synchronous networks. 528-531 - Paul Madeira, Marc-Andre LaCroix, John Hogeboom:
A low jitter clocking strategy for a 7.5-Gb/s SerDes array in 65nm CMOS technology. 532-535
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2025-12-09 23:24 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
