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ORCIDTakuji Miki
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Journal Articles
- 2023
[j13]Takuya Wadatsumi, Kohei Kawai, Rikuu Hasegawa, Kikuo Muramatsu, Hiromu Hasegawa, Takuya Sawada, Takahito Fukushima, Hisashi Kondo, Takuji Miki
, Makoto Nagata:
Experimental Exploration of the Backside ESD Impacts on an IC Chip in Flip Chip Packaging. IEICE Trans. Electron. 106(10): 556-564 (2023)- [j12]Ryozo Takahashi, Takuji Miki, Makoto Nagata:
An Analog Side-Channel Attack on a High-Speed Asynchronous SAR ADC Using Dual Neural Network Technique. IEICE Trans. Electron. 106(10): 565-569 (2023) - 2022
- [j11]Kazuki Monta, Leonidas Katselas, Ferenc Fodor, Takuji Miki, Alkis A. Hatzopoulos, Makoto Nagata, Erik Jan Marinissen:
Testing Embedded Toggle Generation Through On-Chip IR-Drop Measurements. IEEE Des. Test 39(5): 79-87 (2022) - [j10]Takuji Miki, Ryozo Takahashi, Makoto Nagata:
An 11-bit 0.008mm2 charge-redistribution digital-to-analog converter operating at cryogenic temperature for large-scale qubit arrays. IEICE Electron. Express 19(8): 20220099 (2022) - [j9]Makoto Nagata, Takuji Miki, Noriyuki Miura:
Physical Attack Protection Techniques for IC Chip Level Hardware Security. IEEE Trans. Very Large Scale Integr. Syst. 30(1): 5-14 (2022) - 2020
- [j8]Takuji Miki, Makoto Nagata, Hiroki Sonoda, Noriyuki Miura, Takaaki Okidono, Yuuki Araga, Naoya Watanabe, Haruo Shimamoto, Katsuya Kikuchi:
Si-Backside Protection Circuits Against Physical Security Attacks on Flip-Chip Devices. IEEE J. Solid State Circuits 55(10): 2747-2755 (2020) - [j7]Takuji Miki, Noriyuki Miura, Hiroki Sonoda, Kento Mizuta, Makoto Nagata:
A Random Interrupt Dithering SAR Technique for Secure ADC Against Reference-Charge Side-Channel Attack. IEEE Trans. Circuits Syst. II Express Briefs 67-II(1): 14-18 (2020) - 2019
- [j6]Takuji Miki, Noriyuki Miura, Makoto Nagata:
A 0.72pJ/bit 400μm2 Physical Random Number Generator Utilizing SAR Technique for Secure Implementation on Sensor Nodes. IEICE Trans. Electron. 102-C(7): 530-537 (2019) - 2017
- [j5]Takuji Miki, Noriyuki Miura, Kento Mizuta, Shiro Dosho, Makoto Nagata:
A 500 MHz-BW -52.5 dB-THD Voltage-to-Time Converter Utilizing Two-Step Transition Inverter Delay Lines in 28 nm CMOS. IEICE Trans. Electron. 100-C(6): 560-567 (2017) - [j4]Takuji Miki, Toshiaki Ozeki, Jun-ichi Naka:
A 2-GS/s 8-bit Time-Interleaved SAR ADC for Millimeter-Wave Pulsed Radar Baseband SoC. IEEE J. Solid State Circuits 52(10): 2712-2720 (2017) - 2015
- [j3]Takuji Miki, Takashi Morie, Kazuo Matsukawa, Yoji Bando, Takeshi Okumoto, Koji Obata, Shiro Sakiyama, Shiro Dosho:
A 4.2 mW 50 MS/s 13 bit CMOS SAR ADC With SNR and SFDR Enhancement Techniques. IEEE J. Solid State Circuits 50(6): 1372-1381 (2015) - [j2]Noriyuki Miura, Shiro Dosho, Hiroyuki Tezuka, Takuji Miki, Daisuke Fujimoto, Takuya Kiriyama, Makoto Nagata:
A 1 mm Pitch 80 × 80 Channel 322 Hz Frame-Rate Multitouch Distribution Sensor With Two-Step Dual-Mode Capacitance Scan. IEEE J. Solid State Circuits 50(11): 2741-2749 (2015) - 2012
- [j1]Takuji Miki, Takashi Morie, Toshiaki Ozeki, Shiro Dosho:
An 11-b 300-MS/s Double-Sampling Pipelined ADC With On-Chip Digital Calibration for Memory Effects. IEEE J. Solid State Circuits 47(11): 2773-2782 (2012)
Conference and Workshop Papers
- 2024
- [c16]Rikuu Hasegawa, Kazuki Monta, Takuya Wadatsumi, Takuji Miki, Makoto Nagata:
On-Chip Evaluation of Voltage Drops and Fault Occurrence Induced by Si Backside EM Injection. COSADE 2024: 22-37 - 2023
- [c15]Yuya Aoki, Tatsuya Iwata, Takuji Miki, Kazutoshi Kobayashi, Takefumi Yoshikawa:
A 13-bit Radiation-Hardened SAR-ADC with Error Correction by Adaptive Topology Transformation. IRPS 2023: 1-8 - [c14]Takuya Wadatsumi, Kohei Kawai, Rikuu Hasegawa, Kazuki Monta, Takuji Miki, Makoto Nagata:
Characterization of Backside ESD Impacts on Integrated Circuits. IRPS 2023: 1-6 - [c13]Noriyuki Miura, Kotaro Naruse, Jun Shiomi, Yoshihiro Midoh, Tetsuya Hirose, Takaaki Okidono, Takuji Miki, Makoto Nagata:
A Triturated Sensing System. ISSCC 2023: 216-217 - 2022
- [c12]Takuya Wadatsumi, Kohei Kawai, Rikuu Hasegawa, Takuji Miki, Makoto Nagata, Kikuo Muramatsu, Hiromu Hasegawa, Takuya Sawada, Takahito Fukushima, Hisashi Kondo:
Voltage Surges by Backside ESD Impacts on IC Chip in Flip Chip Packaging. IRPS 2022: 14-1 - 2020
- [c11]Takuji Miki, Noriyuki Miura, Hiroki Sonoda, Kento Mizuta, Makoto Nagata:
A Random Interrupt Dithering SAR Technique for Secure ADC against Reference-Charge Side-Channel Attack. ISCAS 2020: 1 - 2019
- [c10]Takuji Miki, Makoto Nagata, Akihiro Tsukioka, Noriyuki Miura, Takaaki Okidono, Yuuki Araga, Naoya Watanabe, Haruo Shimamoto, Katsuya Kikuchi:
Over-the-top Si Interposer Embedding Backside Buried Metal PDN to Reduce Power Supply Impedance of Large Scale Digital ICs. 3DIC 2019: 1-4 - [c9]Takuji Miki, Makoto Nagata, Hiroki Sonoda, Noriyuki Miura, Takaaki Okidono, Yuuki Araga, Naoya Watanabe, Haruo Shimamoto, Katsuya Kikuchi:
A Si-Backside Protection Circuits Against Physical Security Attacks on Flip-Chip Devices. A-SSCC 2019: 25-28 - [c8]Makoto Nagata, Takuji Miki, Noriyuki Miura:
On-Chip Physical Attack Protection Circuits for Hardware Security : Invited Paper. CICC 2019: 1-6 - 2016
- [c7]Takuji Miki, Toshiaki Ozeki, Jun-ichi Naka:
A 2GS/s 8b time-interleaved SAR ADC for millimeter-wave pulsed radar baseband SoC. A-SSCC 2016: 5-8 - [c6]Takuji Miki, Noriyuki Miura, Kento Mizuta, Shiro Dosho, Makoto Nagata:
A 500MHz-BW -52.5dB-THD Voltage-to-Time Converter utilizing a two-step transition inverter. ESSCIRC 2016: 141-144 - [c5]Koji Obata, Kazuo Matsukawa, Takuji Miki, Yusuke Tsukamoto, Koji Sushihara:
A 97.99 dB SNDR, 2 kHz BW, 37.1 µW noise-shaping SAR ADC with dynamic element matching and modulation dither effect. VLSI Circuits 2016: 1-2 - 2014
- [c4]Noriyuki Miura, Shiro Dosho, Satoshi Takaya, Daisuke Fujimoto, Takuya Kiriyama, Hiroyuki Tezuka, Takuji Miki, Hiroto Yanagawa, Makoto Nagata:
12.4 A 1mm-pitch 80×80-channel 322Hz-frame-rate touch sensor with two-step dual-mode capacitance scan. ISSCC 2014: 216-217 - 2013
- [c3]Takashi Morie, Takuji Miki, Kazuo Matsukawa, Yoji Bando, Takeshi Okumoto, Koji Obata, Shiro Sakiyama, Shiro Dosho:
A 71dB-SNDR 50MS/s 4.2mW CMOS SAR ADC by SNR enhancement techniques utilizing noise. ISSCC 2013: 272-273 - 2009
- [c2]Kazuo Matsukawa, Takashi Morie, Yusuke Tokunaga, Shiro Sakiyama, Yosuke Mitani, Masao Takayama, Takuji Miki, Akinori Matsumoto, Koji Obata, Shiro Dosho:
Design methods for pipeline & delta-sigma A-to-D converters with convex optimization. ASP-DAC 2009: 690-695 - 2006
- [c1]Tsutomu Nishimura, Takuji Miki, Hiroaki Sugiura, Yuki Matsumoto, Masatsugu Kobayashi, Toshiyuki Kato, Tsutomu Eda, Hironori Yamauchi:
Configurable multi-processor architecture and its processor element design. ASP-DAC 2006: 124-125
Coauthor Index
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