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2000 – 2009
- 2009
[j3]Tamer Ragheb, Andrew J. Ricketts, Mosin Mondal, Sami Kirolos, Greg M. Link, Vijaykrishnan Narayanan, Yehia Massoud:
Design of Thermally Robust Clock Trees Using Dynamically Adaptive Clock Buffers. IEEE Trans. Circuits Syst. I Regul. Pap. 56-I(2): 374-383 (2009)- 2007
- [c16]Mosin Mondal, Andrew J. Ricketts, Sami Kirolos, Tamer Ragheb, Greg M. Link, Narayanan Vijaykrishnan, Yehia Massoud:
Thermally robust clocking schemes for 3D integrated circuits. DATE 2007: 1206-1211 - [c15]Konrad Malkowski, Greg M. Link, Padma Raghavan, Mary Jane Irwin:
Load Miss Prediction - Exploiting Power Performance Trade-offs. IPDPS 2007: 1-8 - [c14]Mosin Mondal, Andrew J. Ricketts, Sami Kirolos, Tamer Ragheb, Greg M. Link, Narayanan Vijaykrishnan, Yehia Massoud:
Mitigating Thermal Effects on Clock Skew with Dynamically Adaptive Drivers. ISQED 2007: 67-72 - [i1]Greg M. Link, Narayanan Vijaykrishnan:
Hotspot Prevention Through Runtime Reconfiguration in Network-On-Chip. CoRR abs/0710.4764 (2007) - 2006
- [c13]Wei-Lun Hung, Greg M. Link, Yuan Xie, Narayanan Vijaykrishnan, Mary Jane Irwin:
Interconnect and Thermal-aware Floorplanning for 3D Microprocessors. ISQED 2006: 98-104 - [c12]Greg M. Link, Narayanan Vijaykrishnan:
Thermal Trends in Emerging Technologies. ISQED 2006: 625-632 - [c11]S. Conner, Greg M. Link, S. Tobita, Mary Jane Irwin, Padma Raghavan:
Poster reception - Energy/performance modeling for collective communication in 3-D torus cluster networks. SC 2006: 138 - 2005
- [j2]Theocharis Theocharides
, Greg M. Link, Narayanan Vijaykrishnan, Mary Jane Irwin:
Networks on Chip (NoC): Interconnects of Next Generation Systems on Chip. Adv. Comput. 63: 36-92 (2005) - [j1]Eun Jung Kim, Greg M. Link, Ki Hwan Yum, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, Chita R. Das:
A Holistic Approach to Designing Energy-Efficient Cluster Interconnects. IEEE Trans. Computers 54(6): 660-671 (2005) - [c10]Jie S. Hu, Greg M. Link, Johnsy K. John, Shuai Wang, Sotirios G. Ziavras:
Resource-Driven Optimizations for Transient-Fault Detecting SuperScalar Microarchitectures. Asia-Pacific Computer Systems Architecture Conference 2005: 200-214 - [c9]John Conner, Yuan Xie, Mahmut T. Kandemir, Robert P. Dick, Greg M. Link:
FD-HGAC: a hybrid heuristic/genetic algorithm hardware/software co-synthesis framework with fault detection. ASP-DAC 2005: 709-712 - [c8]Greg M. Link, Narayanan Vijaykrishnan:
Hotspot Prevention Through Runtime Reconfiguration in Network-On-Chip. DATE 2005: 648-649 - [c7]Wei-Lun Hung, Greg M. Link, Yuan Xie, Narayanan Vijaykrishnan, Nagu R. Dhanwada, John Conner:
Temperature-Aware Voltage Islands Architecting in System-on-Chip Design. ICCD 2005: 689-696 - [c6]Theo Theocharides, Greg M. Link, Narayanan Vijaykrishnan, Mary Jane Irwin:
Implementing LDPC Decoding on Network-on-Chip. VLSI Design 2005: 134-137 - 2004
- [c5]Matthew Pirretti, Greg M. Link, Richard R. Brooks, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin:
Fault Tolerant Algorithms for Network-On-Chip Interconnect. ISVLSI 2004: 46-51 - [c4]Theo Theocharides, Greg M. Link, Eric J. Swankoski, Narayanan Vijaykrishnan, Mary Jane Irwin, Herman Schmit:
Evaluating Alternative Implementations for LDPC Decoder Check Node Function. ISVLSI 2004: 77-82 - [c3]Theocharis Theocharides, Greg M. Link, Narayanan Vijaykrishnan, Mary Jane Irwin, Vamsi Srikantam:
A generic reconfigurable neural network architecture as a network on chip. SoCC 2004: 191-194 - [c2]Theo Theocharides, Greg M. Link, Narayanan Vijaykrishnan, Mary Jane Irwin, Wayne H. Wolf:
Embedded Hardware Face Detection. VLSI Design 2004: 133- - 2003
- [c1]Eun Jung Kim, Ki Hwan Yum, Greg M. Link, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, Mazin S. Yousif, Chita R. Das:
Energy optimization techniques in cluster interconnects. ISLPED 2003: 459-464
Coauthor Index
aka: Vijaykrishnan Narayanan
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