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ORCIDICCD 2005: San Jose, CA, USA
- 23rd International Conference on Computer Design (ICCD 2005), 2-5 October 2005, San Jose, CA, USA. IEEE Computer Society 2005, ISBN 0-7695-2451-6
Cover
- Title Page.
- Copyright.
Introduction
- Welcome Message.
- Organizing Committee.
- Program Committee.
- Additional Reviewers.
Keynote Presentation
- David A. Patterson:
Latency Lags Bandwidth. 3-6
1.1 Power and Thermal Consideration in Processor Design (I)
- Peng Li, Yangdong Deng, Lawrence T. Pileggi
:
Temperature-Dependent Optimization of Cache Leakage Power Dissipation. 7-12 - Hoang Q. Dao, Bart R. Zeydel, Vojin G. Oklobdzija:
Architectural Considerations for Energy Efficiency. 13-16 - Anahita Shayesteh, Eren Kursun, Timothy Sherwood, Suleyman Sair, Glenn Reinman:
Reducing the Latency and Area Cost of Core Swapping through Shared Helper Engines. 17-23 - Kyeong-Jae Lee, Kevin Skadron, Wei Huang:
Analytical Model for Sensor Placement on Microprocessors. 24-30
1.2 Interconnect Prediction and Optimization
- Qinghua Liu, Malgorzata Marek-Sadowska:
Pre-layout Physical Connectivity Prediction with Application in Clustering-Based Placement. 31-37 - Zion Cien Shen, Chris C. N. Chu, Ying-Meng Li:
Efficient Rectilinear Steiner Tree Construction with Rectilinear Blockages. 38-44 - Seraj Ahmad, Nikhil Jayakumar, Vijay Balasubramanian, Edward Hursey, Sunil P. Khatri, Rabi N. Mahapatra:
X-Routing using Two Manhattan Route Instances. 45-52
1.3 System-Level Architecture
- Li Zhao, Ravi R. Iyer, Srihari Makineni, Laxmi N. Bhuyan, Donald Newell:
Hardware Support for Bulk Data Movement in Server Platforms. 53-60 - Mazen Kharbutli, Yan Solihin:
Counter-Based Cache Replacement Algorithms. 61-68 - Mehrdad Reshadi, Bita Gorjiara, Daniel D. Gajski:
Utilizing Horizontal and Vertical Parallelism with a No-Instruction-Set Compiler for Custom Datapaths. 69-76
Panel Discussion
- Rich Faris, Ken Larsen, Harry Foster, Stuart Swan:
Are Today's Verification Tools Able to Handle Current Design Challenges? 77
2.1 Power aware System Design
- Andi Nourrachmat, Sabino Salerno, Enrico Macii, Massimo Poncino:
Energy-Efficient Color Approximation for Digital LCD Interfaces. 81-86 - Martino Ruggiero, Andrea Acquaviva, Davide Bertozzi, Luca Benini:
Application-Specific Power-Aware Workload Allocation for Voltage Scalable MPSoC Platforms. 87-93 - Vasily G. Moshnyaga, Eiji Morikawa:
LCD Display Energy Reduction by User Monitoring. 94-97 - Kimish Patel, Enrico Macii, Massimo Poncino:
Frame Buffer Energy Optimization by Pixel Prediction. 98-101 - Bo-Cheng Charles Lai, Patrick Schaumont, Wei Qin, Ingrid Verbauwhede:
Energy and Performance Analysis of Mapping Parallel Multithreaded Tasks for An On-Chip Multi-Processor System. 102-104 - Nevine AbouGhazaleh, Bruce R. Childers, Daniel Mossé, Rami G. Melhem:
Near-memory Caching for Improved Energy Consumption. 105-110
2.2 Physical-Aware System-Level Analysis and Synthesis
- Yuanfang Hu, Hongyu Chen, Yi Zhu, Andrew A. Chien, Chung-Kuan Cheng:
Physical Synthesis of Energy-Efficient Networks-on-Chip Through Topology Exploration and Wire Style Optimizationz. 111-118 - Shrirang M. Yardi, Karthik Channakeshava, Michael S. Hsiao, Thomas L. Martin, Dong S. Ha:
A Formal Framework for Modeling and Analysis of System-Level Dynamic Power Management. 119-126 - Soheil Ghiasi:
Efficient Implementation Selection via Time Budgeting Complexity Analysis and Leakage Optimization Case Study. 127-129 - Hang Li, Pu Liu, Zhenyu Qi, Lingling Jin, Wei Wu, Sheldon X.-D. Tan, Jun Yang:
Efficient Thermal Simulation for Run-Time Temperature Tracking and Management. 130-136
2.3 SoC Test Methods
- Anuja Sehgal, Sule Ozev, Krishnendu Chakrabarty:
A Flexible Design Methodology for Analog Test Wrappers in Mixed-Signal SOCs. 137-142 - Gang Zeng, Hideo Ito:
Concurrent Core Test for Test Cost Reduction Using Merged Test Set and Scan Tree. 143-146 - Mango Chia-Tso Chao, Seongmoon Wang, Srimat T. Chakradhar, Kwang-Ting Cheng:
ChiYun Compact: A Novel Test Compaction Technique for Responses with Unknown Values. 147-152 - Yung-Chieh Lin, Feng Lu, Kwang-Ting Cheng:
Accurate Diagnosis of Multiple Faults. 153-156 - Jheng-Syun Yang, Shi-Yu Huang:
Quick Scan Chain Diagnosis Using Signal Profiling. 157-160 - Fang Liu, Sule Ozev:
Fast Hierarchical Process Variability Analysis and Parametric Test Development for Analog/RF Circuits. 161-170
3.1 Reliable Circuit Design
- Song Peng, Rajit Manohar:
Fault Tolerant Asynchronous Adder through Dynamic Self-reconfiguration. 171-179 - Lei Wang:
Error-tolerance memory Microarchitecture via Dynamic Multithreading. 179-184 - Patrick Ndai, Amit Agarwal, Qikai Chen, Kaushik Roy:
A Soft Error Monitor Using Switching Current Detection. 185-192
3.2 High Level Systhesis
- Ernst Martin Witte, Anupam Chattopadhyay, Oliver Schliebusch, David Kammler:
Applying Resource Sharing Algorithms to ADL-driven Automatic ASIP Implementation. 193-199 - Koji Ohashi, Mineo Kaneko:
Statistical Analysis Driven Synthesis of Asynchronous Systems. 200-205 - Nilanjan Banerjee, Arijit Raychowdhury, Swarup Bhunia, Hamid Mahmoodi-Meimand, Kaushik Roy:
Novel Low-Overhead Operand Isolation Techniques for Low-Power Datapath Synthesis. 206-214
3.3 Verification of SoCs with Datapaths and Software
- Namrata Shekhar, Priyank Kalla, Sivaram Gopalakrishnan, Florian Enescu:
Exploiting Vanishing Polynomials for Equivalence Veri.cation of Fixed-Size Arithmetic Datapaths. 215-220 - Marc Boule, Zeljko Zilic:
Incorporating Ef.cient Assertion Checkers into Hardware Emulation. 221-228 - Íñigo Ugarte, Pablo Sanchez:
Assertion Checking of Behavioral Descriptions with Non-linear Solver. 229-231 - Bhanu Pisupati, Geoffrey Brown:
File System Interfaces for Embedded Software Development. 232-238
Keynote Address
- Michael J. Flynn:
Yesterday and Tomorrow: A View on Progress in Computer Design. 239-242
4.1 Low Power Circuit Arhcitecture
- Deepak S. Vijayasarathi, Mehrdad Nourani, Mohammad J. Akhbarizadeh, Poras T. Balsara:
Ripple-Precharge TCAM A Low-Power Solution for Network Search Engines. 243-248 - Milena Vratonjic, Bart R. Zeydel, Vojin G. Oklobdzija:
Low- and Ultra Low-Power Arithmetic Units: Design and Comparison. 249-252 - Muhammad M. Khellah, Maged Ghoneima, James W. Tschanz, Yibin Ye, Nasser A. Kurd, Javed Barkatullah, Srikanth Nimmagadda, Yehea I. Ismail:
A Skewed Repeater Bus Architecture for On-Chip Energy Reduction in Microprocessors. 253-257 - Tetsuya Yamada, Masahide Abe, Yusuke Nitta, Kenji Ogura, Manabu Kusaoke, Makoto Ishikawa, Motokazu Ozawa, Kiwamu Takada, Fumio Arakawa, Osamu Nishii, Toshihiro Hattori:
Low-Power Design of 90-nm SuperH Processor Core. 258-266
4.2 Emerging Design Styles and Applications
- Bradley R. Quinton, Mark R. Greenstreet, Steven J. E. Wilton:
Asynchronous IC Interconnect Network Design and Implementation Using a Standard ASIC Flow. 267-274 - Aswin C. Sankaranarayanan, Rama Chellappa, Ankur Srivastava:
Algorithmic and Architectural Design Methodology for Particle Filters in Hardware. 275-280 - Wei Zhang, Niraj K. Jha:
ALLCN: An Automatic Logic-to-Layout Tool for Carbon Nanotube Based Nanotechnology. 281-288 - Li-Kai Chang, Fu-Chiung Cheng:
Automatic Synthesis of Composable Sequential Quantum Boolean Circuits. 289-296
4.3 Formal Verification - Form Hardware to Software (Invited)
- Franjo Ivancic, Ilya Shlyakhter, Aarti Gupta, Malay K. Ganai, Vineet Kahlon, Chao Wang, Zijiang Yang:
Model Checking C Programs Using F-SOFT. 297-308 - Mark A. Hillebrand, Thomas In der Rieden, Wolfgang J. Paul:
Dealing with I/O Devices in the Context of Pervasive System Verification. 309-316 - Sven Beyer, Peter Böhm, Michael Gerke, Mark A. Hillebrand, Thomas In der Rieden, Steffen Knapp, Dirk Leinenbach, Wolfgang J. Paul:
Towards the Formal Verification of Lower System Layers in Automotive Systems. 317-326
5.1 Cache Memory Architecture
- Prateek Pujara, Aneesh Aggarwal:
Restrictive Compression Techniques to Increase Level 1 Cache Capacity. 327-333 - Jan-Willem van de Waerdt, Stamatis Vassiliadis, Jean-Paul van Itegem, Hans Van Antwerpen:
The TM3270 Media-Processor Data Cache. 334-341 - Luong Dinh Hung, Masahiro Goshima, Shuichi Sakai:
Mitigating Soft Errors in Highly Associative Cache with CAM-based Tag. 342-350
5.2 Gate Timing abd Power Analysis
- Soroush Abbaspour, Hanif Fatemi, Massoud Pedram:
VGTA: Variation Aware Gate Timing Analysis. 351-356 - Felipe Ribeiro Schneider, Renato P. Ribas, Sachin S. Sapatnekar, André Inácio Reis:
Exact lower bound for the number of switches in series to implement a combinational logic cell. 357-362 - Peng Li, Emrah Acar:
A Waveform Independent Gate Model for Accurate Timing Analysis. 363-365 - Fei Hu, Vishwani D. Agrawal:
Enhanced Dual-Transition Probabilistic Power Estimation with Selective Supergate Analysis. 366-372
5.3 Perform Modeling
- Tipp Moseley, Dirk Grunwald, Joshua L. Kihm, Daniel A. Connors:
Methods for Modeling Resource Contention on Simultaneous Multithreading Processors. 373-380 - Carl S. Lebsack, J. Morris Chang:
Using Scratchpad to Exploit Object Locality in Java. 381-386 - Khaled Z. Ibrahim:
Correlation between Detailed and Simplified Simulations in Studying Multiprocessor Architecture. 387-392 - Yue Luo, Lizy Kurian John:
Simulating Commercial Java Throughput Workloads: A Case Study. 393-398
6.1 Low Voltage Design
- Nikhil Jayakumar, Sunil P. Khatri:
Minimum Energy Near-threshold Network of PLA based Design. 399-404 - Jinhui Chen, Lawrence T. Clark, Yu Cao:
Robust Design of High Fan-In/Out Subthreshold Circuits. 405-410 - Sheng-Chih Lin, Navin Srivastava, Kaustav Banerjee:
A Thermally-Aware Methodology for Design-Specific Optimization of Supply and Threshold Voltages in Nanometer Scale ICs. 411-416 - Arijit Raychowdhury, Saibal Mukhopadhyay, Kaushik Roy:
A Feasibility Study of Subthreshold SRAM Across Technology Generations. 417-424
6.2 Physical-Aware Circuit Design
- Azadeh Davoodi, Ankur Srivastava:
Variability-Driven Buffer Insertion Considering Correlations. 425-430 - Valmiki Mukherjee, Saraju P. Mohanty, Elias Kougianos:
A Dual Dielectric Approach for Performance Aware Gate Tunneling Reduction in Combinational Circuits. 431-437 - Andrew B. Kahng, Bao Liu, Qinke Wang:
Supply Voltage Degradation Aware Analytical Placement. 437-443 - Anuradha Agarwal, Ranga Vemuri:
Layout-Aware RF Circuit Synthesis Driven by Worst Case Parasitic Corners. 444-452
6.3 Verification and Test for Sequential Circuits and Delay Fault Models
- Manan Syal, Rajat Arora, Michael S. Hsiao:
Extended Forward Implications and Dual Recurrence Relations to Identify Sequentially Untestable Faults. 453-460 - Qiang Qiang, Chia-Lun Chang, Daniel G. Saab, Jacob A. Abraham:
Case Study of ATPG-based Bounded Model Checking: Verifying USB2.0 IP Core. 461-463 - Maria K. Michael, Kyriakos Christou, Spyros Tragoudas:
Towards finding path delay fault tests with high test efficiency using ZBDDs. 464-467 - Mahilchi Milir Vaseekar Kumar, Spyros Tragoudas:
Quality Transition Fault Tests Suitable for Small Delay Defects. 468-470 - Narendra Devta-Prasanna, Arun Gunda, P. Krishnamurthy, Sudhakar M. Reddy, Irith Pomeranz:
A Novel Method of Improving Transition Delay Fault Coverage Using Multiple Scan Enable Signals. 471-474 - Laung-Terng Wang, Xiaoqing Wen, Po-Ching Hsu, Shianling Wu, Jonhson Guo:
At-Speed Logic BIST Architecture for Multi-Clock Designs. 475-478 - Liyang Lai, Janak H. Patel, Thomas Rinderknecht, Wu-Tung Cheng:
Hardware Ef.cient LBISTWith Complementary Weights. 479-484
7.1 New Memory Technologies (Invited)
- Rick Bailey, Glen Fox, Jarrod Eliason, Marty Depner, Daesig Kim, Edwin Jabillo, John Groat, John Walbert, Scott R. Summerfelt, K. R. Udayakumar, John Rodriquez, Keith Remack, K. Boku, John Gertas:
FRAM Memory Technology - Advantages for Low Power, Fast Write, High Endurance Applications. 485
8.1 High Performance Designs
- Hua Li, Jianzhou Li:
A High Performance Sub-Pipelined Architecture for AES. 491-496 - Hongyu Chen, Rui Shi, Chung-Kuan Cheng, David M. Harris:
Surfliner: A Distortionless Electrical Signaling Scheme for Speed of Light On-Chip Communications. 497-502 - Kazunori Shimizu, Tatsuyuki Ishikawa, Takeshi Ikenaga, Satoshi Goto, Nozomu Togawa:
Partially-Parallel LDPC Decoder Based on High-Efficiency Message-Passing Algorithm. 503-510 - Anatoly I. Grushin:
Fast Minimum and Maximum Selection. 511-518
8.2 Future VLSI Technologies and Their Impact
- Yuh-Fang Tsai, Yuan Xie, Narayanan Vijaykrishnan, Mary Jane Irwin:
Three-Dimensional Cache Design Exploration Using 3DCacti. 519-524 - Kiran Puttaswamy, Gabriel H. Loh:
Implementing Caches in a 3D Technology for High Performance Processors. 525-532 - Wenjing Rao, Alex Orailoglu, Ramesh Karri:
Architectural-Level Fault Tolerant Computation in Nanoelectronic Processors. 533-542
8.3 Architecture for Verifiability (Invited)
- Milo M. K. Martin:
Formal Verification and its Impact on the Snooping versus Directory Protocol Debate. 543-449 - Todd M. Austin, Valeria Bertacco:
Deployment of Better Than Worst-Case Design: Solutions and Needs. 550-558
9.1 Low Power Circuit Architecture (II)
- Hailin Jiang, Malgorzata Marek-Sadowska, Sani R. Nassif:
Benefits and Costs of Power-Gating Technique. 559-566 - Maryam Ashouei, Abhijit Chatterjee, Adit D. Singh, Vivek De:
A Dual-Vt Layout Approach for Statistical Leakage Variability Minimization in Nanometer CMOS. 567-573 - Jente B. Kuang, Hung C. Ngo, Kevin J. Nowka, Jethro C. Law, Rajiv V. Joshi:
A Low-Overhead Virtual Rail Technique for SRAM Leakage Power Reduction. 574-584
9.3 Formal Verification Methods
- Kameshwar Chandrasekar, Michael S. Hsiao:
State Set Management for SAT-based Unbounded Model Checking. 585-590 - Anubhav Gupta, Edmund M. Clarke:
Reconsidering CEGAR: Learning Good Abstractions without Refinement. 591-598 - Nikhil Kikkeri, Peter-Michael Seidel:
Formal Verification of Parametric Multiplicative Division Implementations. 599-602 - Nathaniel Ayewah, Nikhil Kikkeri, Peter-Michael Seidel:
Challenges in the Formal Verification of Complete State-of-the-Art Processors. 603-608
10.1 Power and Thermal Consideration in Processor Design (II)
- Won-Ho Park, Andreas Moshovos, Babak Falsafi:
RECAST: Boosting Tag Line Buffer Coverage in Low-Power High-Level Caches "for Free". 609-616 - Fernando Castro, Daniel Chaver, Luis Piñuel, Manuel Prieto, Francisco Tirado, Michael C. Huang:
Load-Store Queue Management: an Energy-Efficient Design Based on a State-Filtering Mechanism.. 617-624 - Johnsy K. John, Jie S. Hu, Sotirios G. Ziavras:
Optimizing the Thermal Behavior of Subarrayed Data Caches. 625-630 - Dinesh C. Suresh, Banit Agrawal, Walid A. Najjar, Jun Yang:
VALVE: Variable Length Value Encoder for Off-Chip Data Buses.. 631-633 - Sivakumar Velusamy, Wei Huang, John C. Lach, Mircea R. Stan, Kevin Skadron:
Monitoring Temperature in FPGA based SoCs. 634-640
10.2 Instruction Issue, Scheduling and Prediction
- Yongxiang Liu, Gokhan Memik, Glenn Reinman:
Reducing the Energy of Speculative Instruction Schedulers. 641-646 - Marco Antonio Ramírez, Adrián Cristal, Mateo Valero, Alexander V. Veidenbaum, Luís Villa:
A New Pointer-based Instruction Queue Design and Its Power-Performance Evaluation. 647-653 - Joseph J. Sharkey, Kanad Ghose, Dmitry V. Ponomarev, Oguz Ergin:
Power-Efficient Wakeup Tag Broadcast. 654-661 - Rania H. Mameesh, Manoj Franklin:
SST: Symbolic Subordinate Threading. 662-665 - Stefan Bieschewski, Joan-Manuel Parcerisa, Antonio González:
Memory Bank Predictors. 666-670
11.1 Circuit Consideration in Process Design
- Xizhen Xu, Sotirios G. Ziavras:
H-SIMD Machine: Configurable Parallel Computing for Matrix Multiplication. 671-676 - Sri Hari Krishna Narayanan, Guilin Chen, Mahmut T. Kandemir, Yuan Xie:
Temperature-Sensitive Loop Parallelization for Chip Multiprocessors. 677-682 - Brock J. LaMeres, Sunil P. Khatri:
Broadband Impedance Matching for Inductive Interconnect in VLSI Packages. 683-688 - Wei-Lun Hung, Greg M. Link, Yuan Xie, Narayanan Vijaykrishnan, Nagu R. Dhanwada, John Conner:
Temperature-Aware Voltage Islands Architecting in System-on-Chip Design. 689-696
11.2 Logic Optimization
- Nathan Kitchen, Andreas Kuehlmann:
Temporal Decomposition for Logic Optimization. 697-702 - Luis A. Plana, Sam Taylor, Doug A. Edwards:
Attacking Control Overhead to Improve Synthesised Asynchronous Circuit Performance. 703-710 - Yung-Chih Chen, Chun-Yao Wang:
An Improved Approach for AlternativeWires Identi.cation. 711-716
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