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ORCIDBehzad Mesgarzadeh
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2010 – 2019
- 2015
[j6]Amin Ojani, Behzad Mesgarzadeh, Atila Alvandpour:
Monte Carlo-Free Prediction of Spurious Performance for ECDLL-Based Synthesizers. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(1): 273-282 (2015)- 2014
- [j5]Behzad Mesgarzadeh:
Simultaneous switching noise reduction by resonant clock distribution networks. Integr. 47(2): 242-249 (2014) - [j4]Amin Ojani, Behzad Mesgarzadeh, Atila Alvandpour:
Modeling and Analysis of Harmonic Spurs in DLL-Based Frequency Synthesizers. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(11): 3075-3084 (2014) - [c18]Amin Ojani, Behzad Mesgarzadeh, Atila Alvandpour:
A low-power direct IQ upconversion technique based on duty-cycled multi-phase sub-harmonic passive mixers for UWB transmitters. ISIC 2014: 42-45 - [c17]Amin Ojani, Behzad Mesgarzadeh, Atila Alvandpour:
A self-calibration technique for fast-switching frequency-hopped UWB synthesis. MIXDES 2014: 154-159 - 2013
- [j3]Ameya Bhide, Omid Esmailzadeh Najari, Behzad Mesgarzadeh, Atila Alvandpour:
An 8-GS/s 200-MHz Bandwidth 68-mW ΔΣ DAC in 65-nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs 60-II(7): 387-391 (2013) - [c16]Amin Ojani, Behzad Mesgarzadeh, Atila Alvandpour:
A quadrature UWB frequency synthesizer with dynamic settling-time calibration. ISCAS 2013: 2480-2483 - 2012
- [c15]Behzad Mesgarzadeh, Ingemar Söderquist, Atila Alvandpour:
Reliability challenges in avionics due to silicon aging. DDECS 2012: 342-347 - [c14]Amin Ojani, Behzad Mesgarzadeh, Atila Alvandpour:
A DLL-based injection-locked frequency synthesizer for WiMedia UWB. ISCAS 2012: 2027-2030 - [c13]Jonas Fritzin, Behzad Mesgarzadeh, Atila Alvandpour:
A Class-D stage with harmonic suppression and DLL-based phase generation. MWSCAS 2012: 45-48 - [c12]Amin Ojani, Behzad Mesgarzadeh, Atila Alvandpour:
A process variation tolerant DLL-based UWB frequency synthesizer. MWSCAS 2012: 558-561 - 2011
- [c11]Behzad Mesgarzadeh, Iman Esmaeil Zadeh
, Atila Alvandpour:
A multi-segment clocking scheme to reduce on-chip EMI. SoCC 2011: 251-255 - 2010
- [c10]Behzad Mesgarzadeh, Atila Alvandpour:
EMI reduction by resonant clock distribution networks. ISCAS 2010: 977-980
2000 – 2009
- 2009
- [j2]Behzad Mesgarzadeh, Atila Alvandpour:
A Low-Power Digital DLL-Based Clock Generator in Open-Loop Mode. IEEE J. Solid State Circuits 44(7): 1907-1913 (2009) - 2008
- [c9]Behzad Mesgarzadeh, Atila Alvandpour:
A 2-GHz 7-mW digital DLL-based frequency multiplier in 90-nm CMOS. ESSCIRC 2008: 86-89 - 2007
- [j1]Behzad Mesgarzadeh, Martin Hansson, Atila Alvandpour:
Jitter Characteristic in Charge Recovery Resonant Clock Distribution. IEEE J. Solid State Circuits 42(7): 1618-1625 (2007) - 2006
- [c8]Martin Hansson, Behzad Mesgarzadeh, Atila Alvandpour:
1.56 GHz On-chip Resonant Clocking in 130nm CMOS. CICC 2006: 241-244 - [c7]Behzad Mesgarzadeh, Atila Alvandpour:
First-Harmonic Injection-Locked Ring Oscillators. CICC 2006: 733-736 - [c6]Behzad Mesgarzadeh, Atila Alvandpour:
A wide-tuning range 1.8 GHz quadrature VCO utilizing coupled ring oscillators. ISCAS 2006 - [c5]Behzad Mesgarzadeh, Atila Alvandpour:
A 24-mW 0.02-mm2 1.5-GHz DLL-Based Frequency Multiplier in 130-nm CMOS. SoCC 2006: 257-260 - 2005
- [c4]Behzad Mesgarzadeh, Atila Alvandpour:
A study of injection locking in ring oscillators. ISCAS (6) 2005: 5465-5468 - [c3]Anders Edman, Christer Svensson, Behzad Mesgarzadeh:
Synchronous latency-insensitive design for multiple clock domain. SoCC 2005: 83-86 - 2004
- [c2]Behzad Mesgarzadeh:
A CMOS implementation of current-mode min-max circuits and a sample fuzzy application. FUZZ-IEEE 2004: 941-946 - [c1]Behzad Mesgarzadeh, Christer Svensson, Atila Alvandpour:
A new mesochronous clocking scheme for synchronization in SoC. ISCAS (2) 2004: 605-608
Coauthor Index
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