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2010 – 2019
- 2017
[j5]Vinícius Dal Bem, Felipe S. Marranghello, André Inácio Reis, Renato P. Ribas:
SAT-Based Formulation for Logical Capacity Evaluation of VIA-Configurable Structured ASIC. IEEE Trans. Emerg. Top. Comput. 5(2): 247-259 (2017)- 2016
- [b1]Vinícius Dal Bem:
SAT based environment for logical capacity evaluation of via configurable block templates. Universidade Federal do Rio Grande do Sul, Porto Alegre, Brazil, 2016 - 2013
- [j4]Paulo F. Butzen
, Vinícius Dal Bem, André Inácio Reis, Renato P. Ribas:
BTI and HCI first-order aging estimation for early use in standard cell technology mapping. Microelectron. Reliab. 53(9-11): 1360-1364 (2013) - [c7]Lucas Machado, Vinícius Dal Bem, Francesc Moll, Sergio Gómez, Renato P. Ribas, André Inácio Reis:
Logic synthesis for manufacturability considering regularity and lithography printability. ISVLSI 2013: 230-235 - [c6]Caio G. P. Alegretti, Vinícius Dal Bem, Renato P. Ribas, André Inácio Reis:
Analytical logical effort formulation for minimum active area under delay constraints. SBCCI 2013: 1-6 - 2012
- [j3]Paulo F. Butzen, Vinícius Dal Bem, André Inácio Reis, Renato P. Ribas:
Design of CMOS logic gates with enhanced robustness against aging degradation. Microelectron. Reliab. 52(9-10): 1822-1826 (2012) - [c5]Vinícius Dal Bem, André Inácio Reis, Renato P. Ribas:
Lithography analysis of via-configurable transistor-array fabrics. NORCHIP 2012: 1-4 - 2011
- [c4]Felipe S. Marranghello, Vinícius Dal Bem, André Inácio Reis, Renato P. Ribas, Francesc Moll:
Transistor Sizing Analysis of Regular Fabrics. ARCS Workshops 2011 - [c3]Vinícius Dal Bem, Paulo F. Butzen, Felipe S. Marranghello, André Inácio Reis, Renato P. Ribas:
Impact and optimization of lithography-aware regular layout in digital circuit design. ICCD 2011: 279-284 - [c2]Felipe S. Marranghello, Vinícius Dal Bem, André Inácio Reis, Francesc Moll, Renato P. Ribas:
Transistor sizing in lithography-aware regular fabrics. SBCCI 2011: 97-102 - [c1]Vinícius Dal Bem, Paulo F. Butzen, Carlos Eduardo Klock, Vinicius Callegaro, André Inácio Reis, Renato P. Ribas:
Area impact analysis of via-configurable regular fabric for digital integrated circuit design. SBCCI 2011: 103-108 - 2010
- [j2]Paulo F. Butzen, Vinícius Dal Bem, André Inácio Reis, Renato P. Ribas:
Leakage Analysis Considering the Effect of Inter-Cell Wire Resistance for Nanoscaled CMOS Circuits. J. Low Power Electron. 6(1): 192-200 (2010) - [j1]Paulo F. Butzen, Vinícius Dal Bem, André Inácio Reis, Renato P. Ribas:
Transistor network restructuring against NBTI degradation. Microelectron. Reliab. 50(9-11): 1298-1303 (2010)
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