default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDISVLSI 2013: Natal, Brazil
- IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2013, Natal, Brazil, August 5-7, 2013. IEEE Computer Socity 2013, ISBN 978-1-4799-1331-2
- Fernanda Lima Kastensmidt
, Ricardo Reis, Leandro Soares Indrusiak, Gilles Sassatelli:
Message from the general and program chairs. - Manuel d'Abreu:
NAND Flash memory: The driving technology in digital storage - Overview and challenges. 1 - Junghee Lee, Chrysostomos Nicopoulos, Sung Joo Park, Madhavan Swaminathan, Jongman Kim:
Do we need wide flits in Networks-on-Chip? 2-7 - Alexandre M. Amory, Edson I. Moreno, Fernando Moraes, Marcelo Lubaszewski:
Determining the test sources/sinks for NoC TAMs. 8-13 - M. Norazizi Sham Mohd Sayuti, Leandro Soares Indrusiak:
Real-time low-power task mapping in Networks-on-Chip. 14-19 - Alair Dias Junior, Diógenes Cecilio da Silva Júnior:
Using guiding heuristics to improve the dynamic checking of temporal properties in data dominated high-level designs. 20-25 - Jannis Stoppe, Robert Wille, Rolf Drechsler:
Data extraction from SystemC designs using debug symbols and the SystemC API. 26-31 - Manfred Glesner, François Philipp:
Embedded systems design for smart system integration. 32-33 - Carsten Tradowsky, Tanja Harbaum, Shaver Deyerle, Jürgen Becker:
LImbiC: An adaptable architecture description language model for developing an application-specific image processor. 34-39 - Vianney Lapotre, Purushotham Murugappa, Guy Gogniat, Amer Baghdadi, Jean-Philippe Diguet, Jean-Noel Bazin, Michael Hübner:
A reconfigurable multi-standard ASIP-based turbo decoder for an efficient dynamic reconfiguration in a multi-ASIP context. 40-45 - Sudarshan Srinivasan, Rance Rodrigues, Arunachalam Annamalai, Israel Koren, Sandip Kundu:
A study on polymorphing superscalar processor dynamically to improve power efficiency. 46-51 - Hailong Jiao, Volkan Kursun:
Ground gated 8T SRAM cells with enhanced read and hold data stability. 52-57 - Worawit Somha, Hiroyuki Yamauchi, Ma YuYu:
A discussion on SRAM forward/inverse problem analyses for RTN long-tail distributions. 58-63 - Khawar Sarfraz, Volkan Kursun:
Characterization of a low leakage current and high-speed 7T SRAM circuit with wide voltage margins. 64-69 - Mei Hong, Hui Guo, Sri Parameswaran:
Dynamic encryption key design and management for memory data encryption in embedded systems. 70-75 - Ankita Arora, Jude Angelo Ambrose, Jorgen Peddersen, Sri Parameswaran:
A double-width algorithmic balancing to prevent power analysis Side Channel Attacks in AES. 76-83 - Guilherme Flach, Tiago Reimann, Gracieli Posser, Marcelo O. Johann, Ricardo Reis:
Simultaneous gate sizing and Vth assignment using Lagrangian Relaxation and delay sensitivities. 84-89 - Bapi Kar, Susmita Sur-Kolay, Chittaranjan A. Mandal:
STAIRoute: Global routing using monotone staircase channels. 90-95 - Brahim Al Farisi, Elias Vansteenkiste, Karel Bruneel, Dirk Stroobandt:
A novel tool flow for increased routing configuration similarity in multi-mode circuits. 96-101 - Erik Jan Marinissen:
Murphy goes 3D. 102 - Chuan Shan, Dimitri Galayko, François Anceau:
On-chip clock error characterization for clock distribution system. 102-108 - Jimmy Tarrillo, Jorge L. Tonfat, Fernanda Lima Kastensmidt, Ricardo Reis, Florent Bruguier, Morgan Bourree, Pascal Benoit, Lionel Torres:
Using electromagnetic emanations for variability characterization in Flash-based FPGAs. 109-114 - Xin Li, Wulong Liu, Haixiao Du, Yu Wang, Yuchun Ma, Huazhong Yang:
Whitespace-aware TSV arrangement in 3D clock tree synthesis. 115-120 - Yuanqing Cheng, Aida Todri-Sanial, Alberto Bosio, Luigi Dillio, Patrick Girard, Arnaud Virazel, Pascal Vivet, Marc Belleville:
A novel method to mitigate TSV electromigration for 3D ICs. 121-126 - Sudarshan Srinivasan, Raghavan Kumar, Sandip Kundu:
Program phase duration prediction and its application to fine-grain power management. 127-132 - Andrea Manuzzato, Fabio Campi, Davide Rossi, Valentino Liberali, Davide Pandini:
Exploiting body biasing for leakage reduction: A case study. 133-138 - Sungho Park, Ahmed Al-Maashri, Yang Xiao, Kevin M. Irick, Vijaykrishnan Narayanan:
Saliency-driven dynamic configuration of HMAX for energy-efficient multi-object recognition. 139-144 - Lech Józwiak:
HW/SW architecture co-synthesis of ASIP-based MPSoCs for highly- demanding applications. 145-146 - Krishnaji Desai, Kenneth S. Stevens, John O'Leary:
Symbolic verification of timed asynchronous hardware protocols. 147-152 - Guilherme M. Castilhos, Marcelo Mandelli, Guilherme A. Madalozzo, Fernando Moraes:
Distributed resource management in NoC-based MPSoCs with dynamic cluster sizes. 153-158 - Vikram B. Suresh, Sandip Kundu:
On analyzing and mitigating SRAM BER due to random thermal noise. 159-164 - Sudip Roy, Partha Pratim Chakrabarti, Srijan Kumar, Bhargab B. Bhattacharya, Krishnendu Chakrabarty:
Routing-aware resource allocation for mixture preparation in digital microfluidic biochips. 165-170 - Kunal P. Ganeshpure, Sandip Kundu:
On runtime task graph extraction in MPSoC. 171-176 - Walter Luis Tercariol, Richard L. T. Saez, Ivan Carlos Ribeiro do Nascimento:
High and low side high voltage switch with over voltage and over current protection. 177-181 - Matthew Morrison, Nagarajan Ranganathan:
A novel optimization method for reversible logic circuit minimization. 182-187 - Lucas A. Tambara, Fernanda Lima Kastensmidt, Paolo Rech, Tiago R. Balen, Marcelo Lubaszewski:
Neutron-induced single event effects analysis in a SAR-ADC architecture embedded in a mixed-signal SoC. 188-193 - Matthew Lewandowski, Nagarajan Ranganathan, Matthew Morrison:
Behavioral model of integrated qubit gates for quantum reversible logic design. 194-199 - Nagarajan Venkateswaran, Kartik Lakshminarasimhan, Akash Sridhar, Prashanth Thinakaran, Rajagopal Hariharan, Vinesh Srinivasan, Ram Srivatsa Kannan, Aswin Sridharan:
Performance and energy efficient cache system design: Simultaneous execution of multiple applications on heterogeneous cores. 200-205 - Otacilio de Araujo Ramos Neto, Antonio Carlos Cavalcanti, Ruy Alberto Pisani Altafim:
Comparison between three RTL implementations of the multiplicative inverse calculation of galois field elements based on a standard cells library. 206-211 - Mircea Stan:
Breaking power delivery walls using voltage stacking. 212 - Alexsandro Cristovão Bonatto, Altamiro Amadeu Susin:
Memory subsystem architecture design for multimedia applications. 213-214 - Roberto Airoldi, Jari Nurmi:
Design & implementation of software defined radios on a homogeneous multi-processor architecture. 215-216 - Matheus Trevisan Moreira, Ney Laert Vilar Calazans:
Design of standard-cell libraries for asynchronous circuits with the ASCEnD flow. 217-218 - Eduardo Weber Wächter, Alexandre M. Amory, Fernando Gehm Moraes:
Fault recovery communication protocol for NoC-based MPSoCs. 219-220 - Cristina Meinhardt, Ricardo Reis:
A yield-driven regular layout synthesis. 221-222 - Marcelo O. Johann:
Recent advances and challenges in physical design automation. 223 - Mingsong Chen, Saijie Huang, Geguang Pu, Prabhat Mishra:
Branch-and-bound style resource constrained scheduling using efficient structure-aware pruning. 224-229 - Lucas Machado, Vinícius Dal Bem, Francesc Moll, Sergio Gómez, Renato P. Ribas, André Inácio Reis:
Logic synthesis for manufacturability considering regularity and lithography printability. 230-235 - Lucas Machado, Mayler G. A. Martins, Vinicius Callegaro, Renato P. Ribas, André Inácio Reis:
Iterative remapping respecting timing constraints. 236-241
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2025-06-02 21:34 CEST by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
