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Jason Cong
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Publications
- 2023
- [j132]Yuze Chi, Weikang Qiao, Atefeh Sohrabizadeh, Jie Wang, Jason Cong:
Democratizing Domain-Specific Computing. Commun. ACM 66(1): 74-85 (2023) - [j126]Suhail Basalama
, Atefeh Sohrabizadeh
, Jie Wang
, Licheng Guo
, Jason Cong
:
FlexCNN: An End-to-end Framework for Composing CNN Accelerators on FPGA. ACM Trans. Reconfigurable Technol. Syst. 16(2): 23:1-23:32 (2023) - [j124]Licheng Guo
, Yuze Chi
, Jason Lau
, Linghao Song
, Xingyu Tian
, Moazin Khatti
, Weikang Qiao
, Jie Wang
, Ecenur Ustun
, Zhenman Fang
, Zhiru Zhang
, Jason Cong
:
TAPA: A Scalable Task-parallel Dataflow Programming Framework for Modern FPGAs with Co-optimization of HLS and Physical Design. ACM Trans. Reconfigurable Technol. Syst. 16(4): 63:1-63:31 (2023) - [c411]Suhail Basalama, Jie Wang, Jason Cong:
A Comprehensive Automated Exploration Framework for Systolic Array Designs. DAC 2023: 1-6 - 2022
- [c395]Suhail Basalama, Atefeh Sohrabizadeh, Jie Wang, Jason Cong:
A Versatile Systolic Array for Transposed and Dilated Convolution on FPGA. FCCM 2022: 1-2 - [c393]Licheng Guo, Pongstorn Maidee
, Yun Zhou
, Chris Lavin
, Jie Wang, Yuze Chi, Weikang Qiao, Alireza Kaviani, Zhiru Zhang, Jason Cong:
RapidStream: Parallel Physical Implementation of FPGA HLS Designs. FPGA 2022: 1-12 - [i23]Licheng Guo, Yuze Chi, Jason Lau, Linghao Song, Xingyu Tian, Moazin Khatti, Weikang Qiao, Jie Wang, Ecenur Ustun, Zhenman Fang, Zhiru Zhang, Jason Cong:
TAPA: A Scalable Task-Parallel Dataflow Programming Framework for Modern FPGAs with Co-Optimization of HLS and Physical Design. CoRR abs/2209.02663 (2022) - [i22]Yuze Chi, Weikang Qiao, Atefeh Sohrabizadeh, Jie Wang, Jason Cong:
Democratizing Domain-Specific Computing. CoRR abs/2209.02951 (2022) - 2021
- [c381]Yuze Chi, Licheng Guo, Jason Lau
, Young-kyu Choi
, Jie Wang, Jason Cong:
Extending High-Level Synthesis for Task-Parallel Programs. FCCM 2021: 204-213 - [c379]Licheng Guo, Yuze Chi, Jie Wang, Jason Lau
, Weikang Qiao, Ecenur Ustun, Zhiru Zhang
, Jason Cong:
AutoBridge: Coupling Coarse-Grained Floorplanning and Pipelining for High-Frequency HLS Design on Multi-Die FPGAs. FPGA 2021: 81-92 - [c378]Jie Wang, Licheng Guo, Jason Cong:
AutoSA: A Polyhedral Compiler for High-Performance Systolic Arrays on FPGA. FPGA 2021: 93-104 - [c375]Yuze Chi, Licheng Guo, Young-kyu Choi, Jie Wang, Jason Cong:
Extending High-Level Synthesis for Task-Parallel Programs. FPGA 2021: 225 - [c374]Peipei Zhou
, Jiayi Sheng, Cody Hao Yu, Peng Wei, Jie Wang, Di Wu, Jason Cong:
MOCHA: Multinode Cost Optimization in Heterogeneous Clouds with Accelerators. FPGA 2021: 273-279 - [i12]Jie Wang, Jason Cong:
Search for Optimal Systolic Arrays: A Comprehensive Automated Exploration Framework and Lessons Learned. CoRR abs/2111.14252 (2021) - 2020
- [j116]Young-kyu Choi
, Yuze Chi
, Jie Wang, Jason Cong
:
FLASH: Fast, Parallel, and Accurate Simulator for HLS. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(12): 4828-4841 (2020) - [c369]Licheng Guo, Jason Lau
, Yuze Chi, Jie Wang, Cody Hao Yu, Zhe Chen, Zhiru Zhang
, Jason Cong:
Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency. DAC 2020: 1-6 - [c367]Michael Lo
, Zhenman Fang, Jie Wang, Peipei Zhou
, Mau-Chung Frank Chang, Jason Cong:
Algorithm-Hardware Co-design for BQSR Acceleration in Genome Analysis ToolKit. FCCM 2020: 157-166 - [c365]Atefeh Sohrabizadeh, Jie Wang, Jason Cong:
End-to-End Optimization of Deep Learning Applications. FPGA 2020: 133-139 - [c364]Licheng Guo, Jason Lau
, Yuze Chi, Jie Wang, Cody Hao Yu, Zhe Chen, Zhiru Zhang, Jason Cong:
Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency. FPGA 2020: 311 - [c362]Yi-Hsiang Lai, Hongbo Rong, Size Zheng, Weihao Zhang
, Xiuping Cui, Yunshan Jia, Jie Wang, Brendan Sullivan, Zhiru Zhang
, Yun Liang, Youhui Zhang, Jason Cong, Nithin George, Jose Alvarez, Christopher J. Hughes
, Pradeep Dubey:
SuSy: A Programming Model for Productive Construction of High-Performance Systolic Arrays on FPGAs. ICCAD 2020: 73:1-73:9 - [i9]Yuze Chi, Licheng Guo, Young-kyu Choi, Jie Wang, Jason Cong:
Extending High-Level Synthesis for Task-Parallel Programs. CoRR abs/2009.11389 (2020) - [i7]Young-kyu Choi, Yuze Chi, Jie Wang, Licheng Guo, Jason Cong:
When HLS Meets FPGA HBM: Benchmarking and Bandwidth Optimization. CoRR abs/2010.06075 (2020) - 2019
- [c351]Yuze Chi, Young-kyu Choi
, Jason Cong, Jie Wang:
Rapid Cycle-Accurate Simulator for High-Level Synthesis. FPGA 2019: 178-183 - [c349]Yi-Hsiang Lai, Yuze Chi, Yuwei Hu, Jie Wang, Cody Hao Yu, Yuan Zhou, Jason Cong, Zhiru Zhang
:
HeteroCL: A Multi-Paradigm Programming Infrastructure for Software-Defined Reconfigurable Computing. FPGA 2019: 242-251 - 2018
- [c338]Jason Cong, Jie Wang:
Automatic Interior I/O Elimination in Systolic Array Architecture. FCCM 2018: 228 - [c326]Jason Cong, Jie Wang:
PolySA: polyhedral-based systolic array auto-compilation. ICCAD 2018: 117 - [i3]Yuze Chi, Young-kyu Choi, Jason Cong, Jie Wang:
Rapid Cycle-Accurate Simulator for High-Level Synthesis. CoRR abs/1812.07012 (2018) - 2017
- [c309]Jie Wang, Xinfeng Xie
, Jason Cong:
Communication Optimization on GPU: A Case Study of Sequence Alignment Algorithms. IPDPS 2017: 72-81 - 2015
- [c285]Jie Wang, Jason Cong:
Customizable and High Performance Matrix Multiplication Kernel on FPGA (Abstract Only). FPGA 2015: 276

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