"A 0.36 pJ/bit, 12.5 Gb/s forwarded-clock receiver with a sample swapping ..."

Woo-Rham Bae et al. (2014)

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DOI: 10.1109/ESSCIRC.2014.6942118

access: closed

type: Conference or Workshop Paper

metadata version: 2019-09-16

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Woo-Rham Bae, Gyu-Seob Jeong, Kwanseo Park, Sung-Yong Cho, Yoonsoo Kim, Deog-Kyoon Jeong:
A 0.36 pJ/bit, 12.5 Gb/s forwarded-clock receiver with a sample swapping scheme and a half-bit delay line. ESSCIRC 2014: 447-450

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