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Publication search results
found 85 matches
- 2012
- Ahmed Naif M. Alahmadi
, Gordon Russell, Alex Yakovlev
:
Reconfigurable time interval measurement circuit incorporating a programmable gain time difference amplifier. DDECS 2012: 366-371 - Daniel Arbet
, Gábor Gyepes, Juraj Brenkus, Viera Stopjaková
:
OBIST strategy versus parametric test - Efficiency in covering catastrophic faults in active analog filters. DDECS 2012: 193-194 - Efi Arvaniti, Yiorgos Tsiatouhas
:
Low power scan by partitioning and scan hold. DDECS 2012: 262-265 - Ali Azarpeyvand
, Mostafa E. Salehi
, Seid Mehdi Fakhraie:
CIVA: Custom instruction vulnerability analysis framework. DDECS 2012: 318-323 - Ahmed A. El Badry, Mohamed A. Abd El-Ghany
:
CDMA technique for Network-on-Chip. DDECS 2012: 163-166 - Paolo Bernardi
, Lyl M. Ciganda, Michelangelo Grosso
, Ernesto Sánchez, Matteo Sonza Reorda
:
A SBST strategy to test microprocessors' Branch Target Buffer. DDECS 2012: 306-311 - Abdelmajid Bouajila, Abdallah Lakhtel, Johannes Zeppenfeld, Walter Stechele, Andreas Herkersdorf:
A low-overhead monitoring ring interconnect for MPSoC parameter optimization. DDECS 2012: 46-49 - Arkadiusz Bukowiec, Marian Adamski:
Synthesis of Petri nets into FPGA with operation flexible memories. DDECS 2012: 16-21 - Arthur Ceratti, Thiago Copetti, Letícia Maria Bolzani Poehls, Fabian Vargas:
On-chip aging sensor to monitor NBTI effect in nano-scale SRAM. DDECS 2012: 354-359 - Chih-Ping Cheng, Jen-Chieh Liu, Kuo-Hsing Cheng:
Auto-calibration techniques in built-in jitter measurement circuit. DDECS 2012: 248-249 - Martin Chloupek, Ondrej Novák, Jiri Jenícek:
On test time reduction using pattern overlapping, broadcasting and on-chip decompression. DDECS 2012: 300-305 - Mehdi Dehbashi, Görschwin Fey
:
Automated debugging from pre-silicon to post-silicon. DDECS 2012: 324-329 - Roland Dobai, Marcel Baláz:
Genetic method for compressed skewed-load delay test generation. DDECS 2012: 242-247 - Emad Samuel Malki Ebeid
, Davide Quaglia
, Franco Fummi:
Generation of SystemC/TLM code from UML/MARTE sequence diagrams for verification. DDECS 2012: 187-190 - Stephan Eggersglüß, Rene Krenz-Baath, Andreas Glowatz, Friedrich Hapke, Rolf Drechsler
:
A new SAT-based ATPG for generating highly compacted test sets. DDECS 2012: 230-235 - Rouhollah Feghhi, Sasan Naseh:
A 1V, low power, high-gain, 3 - 11 GHz double-balanced CMOS sub-harmonic mixer. DDECS 2012: 179-182 - Petr Fiser, Jan Schmidt:
Improving the iterative power of resynthesis. DDECS 2012: 30-33 - Péter Földesy, Domonkos Gergelyi, Csaba Fuzy, Gergely Károlyi:
Test and configuration architecture of a sub-THz CMOS detector array. DDECS 2012: 101-104 - Martin Gag, Tim Wegner, Ansgar Waschki, Dirk Timmermann
:
Temperature and on-chip crosstalk measurement using ring oscillators in FPGA. DDECS 2012: 201-204 - Maksim Gorev, Vadim Pesonen, Peeter Ellervee
:
Multisine signal generation method for a bioimpedance measurement device. DDECS 2012: 111-114 - Ralph Görgen, Jan-Hendrik Oetjens, Wolfgang Nebel:
Automatic integration of hardware descriptions into system-level models. DDECS 2012: 105-110 - Jacek Gradzki:
Low power balun Design for 1.575 GHz in 90 nm CMOS rechnology. DDECS 2012: 250-253 - Eckhard Grass, Milos Krstic, Xin Fan, Steffen Zeidler:
Asynchronous circuit design: From basics to practical applications. DDECS 2012: 5 - Liang Guang, Ethiopia Nigussie, Juha Plosila
, Jouni Isoaho
, Hannu Tenhunen
:
HLS-DoNoC: High-level simulator for dynamically organizational NoCs. DDECS 2012: 89-94 - Giuseppe Di Guglielmo, Luigi Di Guglielmo, Franco Fummi, Graziano Pravadelli
:
On the use of assertions for embedded-software dynamic verification. DDECS 2012: 330-335 - Gábor Gyepes, Daniel Arbet
, Juraj Brenkus, Viera Stopjaková
:
Application of IDDT test towards increasing SRAM reliability in nanometer technologies. DDECS 2012: 167-170 - M. H. Haghbayan, Saeed Safari
, Zainalabedin Navabi:
Power constraint testing for multi-clock domain SoCs using concurrent hybrid BIST. DDECS 2012: 42-45 - Said Hamdioui:
TSV based 3D stacked ICs: Opportunities and challenges. DDECS 2012: 2 - Matej Hlatký, Valter Martinek, Elena Gramatová:
D&T Presenter - electronic interactive system for design and test education. DDECS 2012: 175-178 - Georg Hofferek:
Automated synthesis and design-error repair of systems. DDECS 2012: 6
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