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Update May 7, 2017: Please note that we had to disable the phrase search operator (.) and the boolean not operator (-) due to technical problems. For the time being, phrase search queries will yield regular prefix search result, and search terms preceded by a minus will be interpreted as regular (positive) search terms.

found 19 matches

• 2001
• 
  Wilfried Daehn:
  Demodulation based testing of off-chip driver performance. ETW 2001: 42-47
• 
  René David, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel:
  On hardware generation of random single input change test sequences. ETW 2001: 117-123
• 
  Rainer Dorsch, Hans-Joachim Wunderlich:
  Reusing scan chains for test pattern decompression. ETW 2001: 124-132
• 
  Magnus Eckersand, Fredrik Franzon, Ken Filliter:
  Using at-speed BIST to test LVDS serializer/deserializer function. ETW 2001: 140-145
• 
  Liquan Fang, Guido Gronthoud, Hans G. Kerkhoff:
  Reducing analogue fault-simulation time by using high-level modelling in dotss for an industrial design. ETW 2001: 61-67
• 
  D. C. L. (Erik) van Geest, Frans G. M. de Jong:
  System-level DFT for consumer products. ETW 2001: 19-24
• 
  Maisaa Khalil, Chantal Robach:
  System level diagnosis - a comparison of two alternative approaches. ETW 2001: 89-95
• 
  Yukiya Miura, Shuichi Seno:
  Internal feedback bridging faults in combinational CMOS circuits: analysis and testing. ETW 2001: 9-16
• 
  Mohsen Nahvi, André Ivanov:
  A packet switching communication-based test access mechanism for system chips. ETW 2001: 81-86
• 
  Oliver Niese, Tiziana Margaria, Andreas Hagerer, Bernhard Steffen, Georg Brune, Werner Goerigk, Hans-Dieter Ide:
  Automated regression testing of CTI-systems. ETW 2001: 51-57
• 
  Jean-Michel Portal, Annie Pérez:
  Analyzing bridging faults impact on EEPROM cell array. ETW 2001: 3-8
• 
  Marco Rona, Gunter Krampl:
  A VHDL-based virtual test concept for pre-silicon test-program debug. ETW 2001: 135-139
• 
  Marcelino B. Santos, Fernando M. Gonçalves, Isabel C. Teixeira, João Paulo Teixeira:
  RTL design validation, DFT and test pattern generation for high defects coverage. ETW 2001: 99-105
• 
  Daniela De Venuto, M. J. Ohletzo, Bruno Riccò:
  On-chip signal level evaluation for mixed-signal ICs using digital window comparators. ETW 2001: 68-72
• 
  Herman J. Vermaak, Hans G. Kerkhoff:
  Reducing the susceptibility of design-for-delay-testability structures to process- and application-induced variations. ETW 2001: 35-41
• 
  Matthew Worsman, Mike W. T. Wong, Yim-Shu Lee:
  The use of equivalent fault analysis to improve static D.C. fault diagnosis - a potentiometric DAC case study. ETW 2001: 73-78
• 
  Joonhwan Yi, John P. Hayes:
  A fault model for function and delay testing. ETW 2001: 27-34
• 
  V. A. Zivkovic, Ronald J. W. T. Tangelder, Hans G. Kerkhoff:
  An implementation for test-time reduction in VLIW transport-triggered architectures. ETW 2001: 106-113
• 
  6th European Test Workshop, ETW 2001, Stockholm, Sweden, May 29 - June 1, 2001. IEEE Computer Society 2001, ISBN 0-7695-1017-5 [contents]