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Publication search results
found 74 matches
- 2014
- Ameer M. S. Abdelhadi, Guy G. F. Lemieux:
Deep and narrow binary content-addressable memories using FPGA-based BRAMs. FPT 2014: 318-321 - Andrei Bara, Xinyu Niu, Wayne Luk:
A dataflow system for anomaly detection and analysis. FPT 2014: 276-279 - Hossein Borhanifar, Seyed Peyman Zolnouri:
Optimize MinMax algorithm to solve Blokus Duo game by HDL. FPT 2014: 362-365 - Fredrik Brosser, Emil Milh, Vilhelm Geijer, Per Larsson-Edefors:
Assessing scrubbing techniques for Xilinx SRAM-based FPGAs in space applications. FPT 2014: 296-299 - Mike Butts:
Logic emulation in the megaLUT era - Moore's Law beats Rent's Rule. FPT 2014: 1 - Zhilei Chai, Haojie Zhou, Zhibin Wang, Dong Wu:
Using C to implement high-efficient computation of dense optical flow on FPGA-accelerated heterogeneous platforms. FPT 2014: 260-263 - Hui Yan Cheah, Suhaib A. Fahmy
, Nachiket Kapre:
Analysis and optimization of a deeply pipelined FPGA soft processor. FPT 2014: 235-238 - Jiahua Chen, Tao Wang, Haoyang Wu, Jian Gong, Xiaoguang Li, Yang Hu, Gaohan Zhang, Zhiwei Li, Junrui Yang
, Songwu Lu:
A high-performance and high-programmability reconfigurable wireless development platform. FPT 2014: 350-353 - Shaoyi Cheng, John Wawrzynek:
Architectural synthesis of computational pipelines with decoupled memory access. FPT 2014: 83-90 - David de la Chevallerie, Jens Korinth, Andreas Koch:
Integrating FPGA-based processing elements into a runtime for parallel heterogeneous computing. FPT 2014: 314-317 - Jason Cong:
Automating customized computing. FPT 2014: 2 - Guohao Dai, Yi Shan, Fei Chen, Yu Wang
, Kun Wang, Huazhong Yang:
Online scheduling for FPGA computation in the Cloud. FPT 2014: 330-333 - Hongyuan Ding, Miaoqing Huang:
Improve memory access for achieving both performance and energy efficiencies on heterogeneous systems. FPT 2014: 91-98 - Andreas Ehliar:
Area efficient floating-point adder and multiplier with IEEE-754 compatible semantics. FPT 2014: 131-138 - Brahim Al Farisi, Karel Heyse, Dirk Stroobandt:
Reducing the overhead of dynamic partial reconfiguration for multi-mode circuits. FPT 2014: 282-283 - Yu Fujita, Koichiro Masuyama, Hideharu Amano:
Image processing by A 0.3V 2MW coarse-grained reconfigurable accelerator CMA-SOTB with a solar battery. FPT 2014: 354-357 - Eric Shun Fukuda, Hiroaki Inoue, Takashi Takenaka, Dahoo Kim, Tsunaki Sadahisa, Tetsuya Asai, Masato Motomura
:
Achieving higher performance of memcached by caching at network interface. FPT 2014: 288-289 - Quentin Gautier, Alexandria Shearer, Janarbek Matai, Dustin Richmond
, Pingfan Meng, Ryan Kastner
:
Real-time 3D reconstruction for FPGAs: A case study for evaluating the performance, area, and programmability trade-offs of the Altera OpenCL SDK. FPT 2014: 326-329 - Marcel Gort, Jason Helge Anderson:
Design re-use for compile time reduction in FPGA high-level synthesis flows. FPT 2014: 4-11 - Yongfu He, Shaojun Wang, Yu Peng, Yeyong Pang, Ning Ma, Jingyue Pang:
High performance relevance vector machine on HMPSoC. FPT 2014: 334-337 - Feng-Hsiung Hsu:
Doing FPGA in a former software company. FPT 2014: 3 - Junying Huang, Colin Yu Lin, Yang Liu, Zhihua Li, Haigang Yang:
Size aware placement for island style FPGAs. FPT 2014: 28-35 - Jiasen Huang, Junyan Ren, Wenbo Yin, Lingli Wang:
No zero padded sparse matrix-vector multiplication on FPGAs. FPT 2014: 290-291 - Tassadaq Hussain, Oscar Palomar
, Osman S. Unsal
, Adrián Cristal
, Eduard Ayguadé
, Mateo Valero
, Shakaib A. Gursal:
AMMC: Advanced Multi-Core Memory Controller. FPT 2014: 292-295 - Gordon Inggs
, Shane T. Fleming, David B. Thomas, Wayne Luk:
Is high level synthesis ready for business? A computational finance case study. FPT 2014: 12-19 - Mark de Jong, Vlad Mihai Sima
, Koen Bertels, David Thomas:
FPGA-accelerated Monte-Carlo integration using stratified sampling and Brownian bridges. FPT 2014: 68-75 - Otávio Alcântara de Lima Júnior, Virginie Fresse, Frédéric Rousseau:
Evaluation of SNMP-like protocol to manage a NoC emulation platform. FPT 2014: 199-206 - Takuya Kajiwara, Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morituro Kuga, Toshinori Sueyoshi:
A novel three-dimensional FPGA architecture with high-speed serial communication links. FPT 2014: 306-309 - Server Kasap
, Soydan Redif
:
Novel reconfigurable hardware implementation of polynomial matrix/vector multiplications. FPT 2014: 243-247 - Akira Kojima:
FPGA implementation of Blokus Duo player using hardware/software co-design. FPT 2014: 378-381
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