• case-insensitive prefix search: default
  e.g., sig matches "SIGIR" as well as "signal"
• exact word search: append dollar sign ($) to word
  e.g., graph$ matches "graph", but not "graphics"
• boolean and: separate words by space
  e.g., codd model
• boolean or: connect words by pipe symbol (|)
  e.g., graph|network

Update May 7, 2017: Please note that we had to disable the phrase search operator (.) and the boolean not operator (-) due to technical problems. For the time being, phrase search queries will yield regular prefix search result, and search terms preceded by a minus will be interpreted as regular (positive) search terms.

found 55 matches

• 1996
• 
  Nidhi Agrawal, Parul Agarwal, C. P. Ravikumar:
  Efficient Delay Test Generation for Modular Circuits. Great Lakes Symposium on VLSI 1996: 220-
• 
  Prakash Arunachalam, Jacob A. Abraham, Manuel A. d'Abreu:
  A Hierarchal Approach for Power Reduction in VLSI Chips. Great Lakes Symposium on VLSI 1996: 182-
• 
  Valeria Bertacco, Maurizio Damiani:
  Boolean Function Representation Using Parallel-Access Diagrams. Great Lakes Symposium on VLSI 1996: 112-117
• 
  Manjit Borah, Robert Michael Owens, Mary Jane Irwin:
  Recent Developments in Performance Driven Steiner Routing: An Overview. Great Lakes Symposium on VLSI 1996: 137-142
• 
  Bradley S. Carlson, C. Y. Roger Chen, Dikran S. Meliksetian:
  Transistor Chaining in CMOS Leaf Cells of Planar Topology. Great Lakes Symposium on VLSI 1996: 194-199
• 
  Yun-Nan Chang, Ching-Yi Wang, Keshab K. Parhi:
  Loop-List Scheduling for Heterogeneous Functional Units. Great Lakes Symposium on VLSI 1996: 2-7
• 
  Chantana Chantrapornchai, Sissades Tongsima, Edwin Hsing-Mean Sha:
  Rapid Prototyping for Fuzzy Systems. Great Lakes Symposium on VLSI 1996: 234-239
• 
  Guangqiu Chen, Hidetoshi Onodera, Keikichi Tamaru:
  Timing and Power Optimization by Gate Sizing Considering False Paths. Great Lakes Symposium on VLSI 1996: 154-
• 
  Pong P. Chu:
  A Reprogrammable FPGA-Based ATM Traffic Generator. Great Lakes Symposium on VLSI 1996: 35-38
• 
  José G. Delgado-Frias, Jabulani Nyathi, Chester L. Miller, Douglas H. Summerville:
  A VLSI Interconnection Network Router Using a D-CAM with Hidden Refresh. Great Lakes Symposium on VLSI 1996: 246-251
• 
  Luc Desormeaux, Valek Szwarc, John H. Lodge:
  A High-Speed, Real-to-Quadrature Converter with Filtering and Decimation. Great Lakes Symposium on VLSI 1996: 252-255
• 
  Hormoz Djahanshahi, Majid Ahmadi, Graham A. Jullien, William C. Miller:
  Design and VLSI Implementation of a Unified Synapse-Neuron Architecture. Great Lakes Symposium on VLSI 1996: 228-233
• 
  Masato Edahiro, Richard J. Lipton:
  Clock Buffer Placement Algorithm for Wire-Delay-Dominated Timing Model. Great Lakes Symposium on VLSI 1996: 143-147
• 
  Kent L. Einspahr, Sharad C. Seth, Vishwani D. Agrawal:
  Improving Circuit Testability by Clock Control. Great Lakes Symposium on VLSI 1996: 288-293
• 
  Emad N. Farag, Mohamed I. Elmasry:
  Low-Power Implementation of Discrete Cosine Transform. Great Lakes Symposium on VLSI 1996: 174-177
• 
  Fabrizio Ferrandi, Franco Fummi, Enrico Macii, Massimo Poncino, Donatella Sciuto:
  Test Generation for Networks of Interacting FSMs Using Symbolic Techniques. Great Lakes Symposium on VLSI 1996: 208-213
• 
  Joseph L. Ganley, James P. Cohoon:
  A Provably Good Moat Routing Algorithm. Great Lakes Symposium on VLSI 1996: 86-85
• 
  Gary William Grewal:
  A Global Mode Instruction Minimization Technique for Embedded DSPs. Great Lakes Symposium on VLSI 1996: 18-
• 
  Laura Heinrich-Litan, Paul Molitor, Dirk Möller:
  Least Upper Bounds on the Sizes of Symmetric Variable Order based OBDDs. Great Lakes Symposium on VLSI 1996: 126-
• 
  Moazzem Hossain, Bala Thumma, Sunil Ashtaputre:
  A New Faster Algorithm for Iterative Placement Improvement. Great Lakes Symposium on VLSI 1996: 44-49
• 
  Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen:
  On Verifying the Correctness of Retimed Circuits. Great Lakes Symposium on VLSI 1996: 277-
• 
  Jai-Sop Hyun, Kwang Sub Yoon:
  A 3V-50MHz Analog CMOS Current-Mode High Frequency Filter with a Negative Resistance Load. Great Lakes Symposium on VLSI 1996: 260-
• 
  Anthony D. Johnson:
  On Locally Optimal Breaking of Complex Cyclic Vertical Constraints in VLSI Channel Routing. Great Lakes Symposium on VLSI 1996: 92-95
• 
  Ayman I. Kayssi:
  Macromodeling C- and RC-loaded CMOS inverters for timing analysis. Great Lakes Symposium on VLSI 1996: 272-276
• 
  Seokjin Kim, Ramalingam Sridhar:
  Self-Timed Mesochronous Interconnection for High-Speed VLSI Systems. Great Lakes Symposium on VLSI 1996: 122-125
• 
  Kevin A. Kwiat, Warren Debany, Salim Hariri:
  Software Fault Tolerance Using Dynamically Reconfigurable FPGAs. Great Lakes Symposium on VLSI 1996: 39-
• 
  John Lillis, Chung-Kuan Cheng, Ting-Ting Y. Lin:
  Simultaneous Routing and Buffer Insertion for High Performance Interconnect. Great Lakes Symposium on VLSI 1996: 148-153
• 
  Mario Alberto López, Dinesh P. Mehta:
  Partitioning Algorithms for Corner Stitching. Great Lakes Symposium on VLSI 1996: 200-
• 
  James Loy, Atul Garg, Mukkai S. Krishnamoorthy, John F. McDonald:
  Chip Pad Migration is a Key Component to High Performance MCM Design. Great Lakes Symposium on VLSI 1996: 96-99
• 
  Enrico Macii, Massimo Poncino:
  Exact Computation of the Entropy of a Logic Circuit. Great Lakes Symposium on VLSI 1996: 162-167

skipping 25 more matches