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Yuchun Ma
Publications
- 2014
- [i1]Bei Yu, Sheqin Dong, Yuchun Ma, Tao Lin, Yu Wang, Song Chen, Satoshi Goto:
Network flow-based simultaneous retiming and slack budgeting for low power design. CoRR abs/1402.2460 (2014) - 2011
- [c40]Bei Yu, Sheqin Dong, Yuchun Ma, Tao Lin, Yu Wang, Song Chen, Satoshi Goto:
Network flow-based simultaneous retiming and slack budgeting for low power design. ASP-DAC 2011: 473-478 - [c37]Tao Lin, Sheqin Dong, Song Chen, Yuchun Ma, Ou He, Satoshi Goto:
Novel and efficient min cut based voltage assignment in gate level. ISQED 2011: 150-155 - 2006
- [j7]Song Chen, Sheqin Dong, Xianlong Hong, Yuchun Ma, Chung-Kuan Cheng:
VLSI Block Placement With Alignment Constraints. IEEE Trans. Circuits Syst. II Express Briefs 53-II(8): 622-626 (2006) - 2005
- [j6]Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Chung-Kuan Cheng, Jun Gu:
Buffer planning as an Integral part of floorplanning with consideration of routing congestion. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(4): 609-621 (2005) - [c14]Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Chung-Kuan Cheng:
Performance constrained floorplanning based on partial clustering [IC layout]. ISCAS (2) 2005: 1863-1866 - [c13]Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Chung-Kuan Cheng:
VLSI block placement with alignment constraints based on corner block list. ISCAS (6) 2005: 6222-6225 - [c12]Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Chung-Kuan Cheng:
Buffer Planning Algorithm Based on Partial Clustered Floorplanning. ISQED 2005: 213-219 - [c11]Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Chung-Kuan Cheng:
Floorplanning with Consideration of White Space Resource Distribution for Repeater Planning. ISQED 2005: 628-633 - 2004
- [j4]Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Yici Cai, Chung-Kuan Cheng, Jun Gu:
A buffer planning algorithm for chip-level floorplanning. Sci. China Ser. F Inf. Sci. 47(6): 763-776 (2004) - [j3]Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Chung-Kuan Cheng, Jun Gu:
Fast Evaluation of Bounded Slice-Line Grid. J. Comput. Sci. Technol. 19(6): 973-980 (2004) - [c10]Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Yici Cai, Chung-Kuan Cheng, Jun Gu:
A buffer planning algorithm with congestion optimization. ASP-DAC 2004: 615-620 - [c9]Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Yici Cai, Chung-Kuan Cheng, Jun Gu:
Buffer allocation algorithm with consideration of routing congestion. ASP-DAC 2004: 621-623 - 2003
- [c8]Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Yici Cai, Chung-Kuan Cheng, Jun Gu:
A buffer planning algorithm based on dead space redistribution. ASP-DAC 2003: 435-438 - [c7]Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Yici Cai, Chung-Kuan Cheng, Jun Gu:
Dynamic global buffer planning optimization based on detail block locating and congestion analysis. DAC 2003: 806-811 - [c6]Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Song Chen, Chung-Kuan Cheng, Jun Gu:
Arbitrary convex and concave rectilinear block packing based on corner block list. ISCAS (5) 2003: 493-496 - [c5]Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Yici Cai, Chung-Kuan Cheng, Jun Gu:
Evaluating a bounded slice-line grid assignment in O(nlogn) time. ISCAS (4) 2003: 708-711 - [c4]Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Yici Cai, Chung-Kuan Cheng, Jun Gu:
An integrated floorplanning with an efficient buffer planning algorithm. ISPD 2003: 136-142
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