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2020 – today
- 2021
[j80]Sung-Hao Wang
, Yu-Kai Huang, Ching-Yuan Chen, Li-Yang Tang, Yen-Fu Tu, Po-Chih Chang, Chia-Fone Lee, Chia-Hsiang Yang, Chung-Chih Hung, Chien-Hao Liu, Ming-Dou Ker, Chung-Yu Wu:
Design of a Bone-Guided Cochlear Implant Microsystem With Monopolar Biphasic Multiple Stimulations and Evoked Compound Action Potential Acquisition and Its In Vivo Verification. IEEE J. Solid State Circuits 56(10): 3062-3076 (2021)- [j79]Chia-Chi Hsieh, Ming-Dou Ker:
Monopolar Biphasic Stimulator With Discharge Function and Negative Level Shifter for Neuromodulation SoC Integration in Low-Voltage CMOS Process. IEEE Trans. Biomed. Circuits Syst. 15(3): 568-579 (2021) - [c94]Chao-Yang Chen, Jian-Hsing Lee, Karuna Nidhi, Tzer-Yaa Bin, Geeng-Lih Lin, Ming-Dou Ker:
Study on the Guard Rings for Latchup Prevention between HV-PMOS and LV-PMOS in a 0.15-µm BCD Process. IRPS 2021: 1-4 - [c93]Shane Harrigan, Sonya A. Coleman, Ming-Dou Ker, Pratheepan Yogarajah, Zheng Fang, Chengdong Wu:
ROT-Harris: A Dynamic Approach to Asynchronous Interest Point Detection. MVA 2021: 1-6 - [c92]Han-Sheng Huang, Ming-Dou Ker:
Design of 2xVDD-Tolerant Power-Rail ESD Clamp Circuit Against False Trigger During Fast Power-ON Events. VLSI-DAT 2021: 1-4 - 2020
- [j78]Ting-Yang Yen, Ming-Dou Ker:
Design of Dual-Mode Stimulus Chip With Built-In High Voltage Generator for Biomedical Applications. IEEE Trans. Biomed. Circuits Syst. 14(5): 961-970 (2020) - [j77]Shiau-Pin Lin, Ming-Dou Ker:
Design of Stage-Selective Negative Voltage Generator to Improve On-Chip Power Conversion Efficiency for Neuron Stimulation. IEEE Trans. Circuits Syst. 67-I(11): 4122-4131 (2020) - [c91]Sung-Hao Wang, Yu-Kai Huang, Ching-Yuan Chen, Chia-Fone Lee, Chia-Hsiang Yang, Chung-Chih Hung, Chien-Hao Liu, Ming-Dou Ker, Chung-Yu Wu:
Improved Design and In Vivo Animal Tests of Bone-Guided Cochlear Implant Microsystem with Monopolar Biphasic Multiple Stimulation and Neural Action Potential Acquisition. A-SSCC 2020: 1-4 - [c90]Yi-Hui Wu, Yi-Huan Ou-Yang, Chiung-Chu Chen, Chen-Yi Lee, Chung-Yu Wu, Ming-Dou Ker:
Miniaturized Intracerebral Potential Recorder for Long-Term Local Field Potential of Deep Brain Signals. EMBC 2020: 5188-5191 - [c89]Chao-Yang Ke, Ming-Dou Ker:
Over-Voltage Protection on the CC Pin of USB Type-C Interface against Electrical Overstress Events. IRPS 2020: 1-5
2010 – 2019
- 2019
- [j76]Ming-Dou Ker, Maurizio Valle, Matthew L. Johnston:
Guest Editorial: Special Issue on Selected Papers From IEEE ISCAS 2019. IEEE Trans. Biomed. Circuits Syst. 13(6): 1125-1127 (2019) - [j75]Xin-Hong Qian, Yi-Chung Wu, Tzu-Yi Yang, Cheng-Hsiang Cheng, Hsing-Chien Chu, Wan-Hsueh Cheng, Ting-Yang Yen, Tzu-Han Lin, Yung-Jen Lin, Yu-Chi Lee, Jia-Heng Chang, Shih-Ting Lin, Shang-Hsuan Li, Tsung-Chen Wu, Chien-Chang Huang, Sung-Hao Wang, Chia-Fone Lee, Chia-Hsiang Yang, Chung-Chih Hung, Tai-Shih Chi, Chien-Hao Liu, Ming-Dou Ker, Chung-Yu Wu:
Design and In Vivo Verification of a CMOS Bone-Guided Cochlear Implant Microsystem. IEEE Trans. Biomed. Eng. 66(11): 3156-3167 (2019) - [j74]Chi-Wei Liu, Yi-Lun Chen, Pei-Chun Liao, Shiau-Pin Lin, Ting-Wei Wang, Ming-Jie Chung, Po-Hung Chen, Ming-Dou Ker, Chung-Yu Wu:
An 82.9%-Efficiency Triple-Output Battery Management Unit for Implantable Neuron Stimulator in 180-nm Standard CMOS. IEEE Trans. Circuits Syst. II Express Briefs 66-II(5): 788-792 (2019) - [j73]Zhicong Luo, Li-Chin Yu, Ming-Dou Ker:
An Efficient, Wide-Output, High-Voltage Charge Pump With a Stage Selection Circuit Realized in a Low-Voltage CMOS Process. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(9): 3437-3444 (2019) - [c88]Chun-Cheng Chen, Ming-Dou Ker:
Investigation on Latch-Up Path Between I/O PMOS and Core PMOS in a 0.18-μm CMOS Process. IRPS 2019: 1-4 - [c87]Tao-Yi Hung, Ming-Dou Ker:
ESD Protection Design of High-Linearity SPDT CMOS T/R Switch for Cellular Applications. ISCAS 2019: 1-5 - 2018
- [j72]Zhicong Luo, Ming-Dou Ker:
A High-Voltage-Tolerant and Power-Efficient Stimulator With Adaptive Power Supply Realized in Low-Voltage CMOS Process for Implantable Biomedical Applications. IEEE J. Emerg. Sel. Topics Circuits Syst. 8(2): 178-186 (2018) - [j71]Cheng-Hsiang Cheng, Ping-Yuan Tsai, Tzu-Yi Yang, Wan-Hsueh Cheng, Ting-Yang Yen, Zhicong Luo, Xin-Hong Qian, Zhi-Xin Chen, Tzu-Han Lin, Wei-Hong Chen, Wei-Ming Chen, Sheng-Fu Liang, Fu-Zen Shaw, Cheng-Siu Chang, Yue-Loong Hsin, Chen-Yi Lee, Ming-Dou Ker, Chung-Yu Wu:
A Fully Integrated 16-Channel Closed-Loop Neural-Prosthetic CMOS SoC With Wireless Power and Bidirectional Data Telemetry for Real-Time Efficient Human Epileptic Seizure Control. IEEE J. Solid State Circuits 53(11): 3314-3326 (2018) - [j70]Wen-Chieh Chen, Ming-Dou Ker:
Surge protection design with surge-to-digital converter for microelectronic circuits and systems. Microelectron. Reliab. 88-90: 2-5 (2018) - [c86]Shiau-Pin Lin, Ming-Dou Ker:
Design of Multiple-Charge-Pump System for Implantable Biomedical Applications. BioCAS 2018: 1-4 - [c85]Chia-Chi Hsieh, Ming-Dou Ker:
Design of Multi-Channel Monopolar Biphasic Stimulator for Implantable Biomedical Applications. MWSCAS 2018: 1-4 - 2017
- [j69]Ting-Chou Lu, Ming-Dou Ker, Hsiao-Wen Zan, Jen-Chieh Liu, Yu Lee:
A 8 Phases 192MHz Crystal-Less Clock Generator with PVT Calibration. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 100-A(1): 275-282 (2017) - [j68]Ting-Chou Lu, Ming-Dou Ker, Hsiao-Wen Zan:
An Ultra-Low Voltage CMOS Voltage Controlled Oscillator with Process and Temperature Compensation. IEICE Trans. Electron. 100-C(8): 675-683 (2017) - [j67]Chun-Yu Lin, Rui-Hong Liu, Ming-Dou Ker:
Design of 2.4-GHz T/R switch with embedded ESD protection devices in CMOS process. Microelectron. Reliab. 78: 258-266 (2017) - [j66]Zhicong Luo, Ming-Dou Ker, Tzu-Yi Yang, Wan-Hsueh Cheng:
A Digitally Dynamic Power Supply Technique for 16-Channel 12 V-Tolerant Stimulator Realized in a 0.18- μm 1.8-V/3.3-V Low-Voltage CMOS Process. IEEE Trans. Biomed. Circuits Syst. 11(5): 1087-1096 (2017) - [j65]Zhicong Luo, Ming-Dou Ker, Wan-Hsueh Cheng, Ting-Yang Yen:
Regulated Charge Pump With New Clocking Scheme for Smoothing the Charging Current in Low Voltage CMOS Process. IEEE Trans. Circuits Syst. I Regul. Pap. 64-I(3): 528-536 (2017) - [c84]Chung-Yu Wu, Cheng-Hsiang Cheng, Yi-Huan Ou-Yang, Chiung-Ghu Chen, Wei-Ming Chen, Ming-Dou Ker, Chen-Yi Lee, Sheng-Fu Liang, Fu-Zen Shaw:
Design considerations and clinical applications of closed-loop neural disorder control SoCs. ASP-DAC 2017: 295-298 - 2016
- [j64]Zhicong Luo, Ming-Dou Ker:
A High-Voltage-Tolerant and Precise Charge-Balanced Neuro-Stimulator in Low Voltage CMOS Process. IEEE Trans. Biomed. Circuits Syst. 10(6): 1087-1099 (2016) - [c83]Jie-Ting Chen, Chun-Yu Lin, Rong-Kun Chang, Ming-Dou Ker, Tzu-Chien Tzeng, Tzu-Chiang Lin:
ESD protection design for high-speed applications in CMOS technology. MWSCAS 2016: 1-4 - [c82]Zhicong Luo, Ming-Dou Ker:
Design of high-voltage-tolerant level shifter in low voltage CMOS process for neuro stimulator. NEWCAS 2016: 1-4 - 2015
- [c81]Seian-Feng Liao, Kai-Neng Tang, Ming-Dou Ker, Jia-Rong Yeh, Hwa-Chyi Chiou, Yeh-Jen Huang, Chun-Chien Tsai, Yeh-Ning Jou, Geeng-Lih Lin:
Impact of guard ring layout on the stacked low-voltage PMOS for high-voltage ESD protection. ECCTD 2015: 1-4 - [c80]Hui-Wen Tsai, Ming-Dou Ker:
Compensation circuit with additional junction sensor to enhance latchup immunity for CMOS integrated circuits. ECCTD 2015: 1-4 - [c79]Chia-Tsen Dai, Ming-Dou Ker:
ESD protection design with stacked low-voltage devices for high-voltage pins of battery-monitoring IC. SoCC 2015: 380-383 - [c78]Federico A. Altolaguirre, Ming-Dou Ker:
Active ESD protection for input transistors in a 40-nm CMOS process. VLSI-DAT 2015: 1-4 - 2014
- [j63]Wei-Ming Chen, Herming Chiueh, Tsan-Jieh Chen, Chia-Lun Ho, Chi Jeng, Ming-Dou Ker, Chun-Yu Lin, Ya-Chun Huang, Chia-Wei Chou, Tsun-Yuan Fan, Ming-Seng Cheng, Yue-Loong Hsin, Sheng-Fu Liang, Yu-Lin Wang, Fu-Zen Shaw, Yu-Hsing Huang, Chia-Hsiang Yang, Chung-Yu Wu:
A Fully Integrated 8-Channel Closed-Loop Neural-Prosthetic CMOS SoC for Real-Time Epileptic Seizure Control. IEEE J. Solid State Circuits 49(1): 232-247 (2014) - [j62]Po-Yen Chiu, Ming-Dou Ker:
Metal-layer capacitors in the 65 nm CMOS process and the application for low-leakage power-rail ESD clamp circuit. Microelectron. Reliab. 54(1): 64-70 (2014) - [j61]Ming-Dou Ker, Wan-Yen Lin, Cheng-Cheng Yen:
SCR-based transient detection circuit for on-chip protection design against system-level electrical transient disturbance. Microelectron. Reliab. 54(1): 71-78 (2014) - [j60]Che-Hao Chuang, Ming-Dou Ker:
On-Chip Transient Voltage Suppressor Integrated With Silicon-Based Transceiver IC for System-Level ESD Protection. IEEE Trans. Ind. Electron. 61(10): 5615-5621 (2014) - [c77]Kuan-Yu Lin, Ming-Dou Ker, Chun-Yu Lin:
A high-voltage-tolerant stimulator realized in the low-voltage CMOS process for cochlear implant. ISCAS 2014: 237-240 - [c76]Li-Wei Chu, Chun-Yu Lin, Ming-Dou Ker, Ming-Hsiang Song, Jeng-Chou Tseng, Chewnpu Jou, Ming-Hsien Tsai:
ESD protection design for wideband RF applications in 65-nm CMOS process. ISCAS 2014: 1480-1483 - [c75]Federico A. Altolaguirre, Ming-Dou Ker:
Power-rail ESD clamp circuit with embedded-trigger SCR device in a 65-nm CMOS process. MWSCAS 2014: 250-253 - 2013
- [j59]Chih-Ting Yeh, Ming-Dou Ker:
PMOS-based power-rail ESD clamp circuit with adjustable holding voltage controlled by ESD detection circuit. Microelectron. Reliab. 53(2): 208-214 (2013) - [j58]Chun-Yu Lin, Wei-Ling Chen, Ming-Dou Ker:
Implantable Stimulator for Epileptic Seizure Suppression With Loading Impedance Adaptability. IEEE Trans. Biomed. Circuits Syst. 7(2): 196-203 (2013) - [j57]Ming-Dou Ker, Po-Yen Chiu:
Design of 2 × VDD-Tolerant I/O Buffer With PVT Compensation Realized by Only 1 × VDD Thin-Oxide Devices. IEEE Trans. Circuits Syst. I Regul. Pap. 60-I(10): 2549-2560 (2013) - [c74]Federico A. Altolaguirre, Ming-Dou Ker:
Low-leakage power-rail ESD clamp circuit with gated current mirror in a 65-nm CMOS technology. ISCAS 2013: 2638-2641 - [c73]Wei-Ming Chen, Herming Chiueh, Tsan-Jieh Chen, Chia-Lun Ho, Chi Jeng, Shun-Ting Chang, Ming-Dou Ker, Chun-Yu Lin, Ya-Chun Huang, Chia-Wei Chou, Tsun-Yuan Fan, Ming-Seng Cheng, Sheng-Fu Liang, Tzu-Chieh Chien, Sih-Yen Wu, Yu-Lin Wang, Fu-Zen Shaw, Yu-Hsing Huang, Chia-Hsiang Yang, Jin-Chern Chiou, Chih-Wei Chang, Lei-Chun Chou, Chung-Yu Wu:
A fully integrated 8-channel closed-loop neural-prosthetic SoC for real-time epileptic seizure control. ISSCC 2013: 286-287 - [c72]Po-Yen Chiu, Ming-Dou Ker:
Design of 2×VDD logic gates with only 1×VDD devices in nanoscale CMOS technology. SoCC 2013: 33-36 - [c71]Federico A. Altolaguirre, Ming-Dou Ker:
Ultra-low-leakage power-rail ESD clamp circuit in a 65-nm CMOS technology. VLSI-DAT 2013: 1-4 - [c70]Hui-Wen Tsai, Ming-Dou Ker, Yi-Sheng Liu, Ming-Nan Chuang:
Analysis and solution to overcome EOS failure induced by latchup test in a high-voltage integrated circuits. VLSI-DAT 2013: 1-4 - [c69]Chih-Ting Yeh, Ming-Dou Ker:
Area-efficient power-rail ESD clamp circuit with SCR device embedded into ESD-transient detection circuit in a 65nm CMOS process. VLSI-DAT 2013: 1-4 - 2012
- [j56]Chih-Ting Yeh, Ming-Dou Ker:
Study of intrinsic characteristics of ESD protection diodes for high-speed I/O applications. Microelectron. Reliab. 52(6): 1020-1030 (2012) - [j55]Chun-Yu Lin, Tang-Long Chang, Ming-Dou Ker:
Investigation on CDM ESD events at core circuits in a 65-nm CMOS process. Microelectron. Reliab. 52(11): 2627-2631 (2012) - [j54]Chih-Ting Yeh, Ming-Dou Ker:
New Design of 2 x VDD-Tolerant Power-Rail ESD Clamp Circuit for Mixed-Voltage I/O Buffers in 65-nm CMOS Technology. IEEE Trans. Circuits Syst. II Express Briefs 59-II(3): 178-182 (2012) - [j53]Ming-Dou Ker, Cheng-Cheng Yen:
New 4-Bit Transient-to-Digital Converter for System-Level ESD Protection in Display Panels. IEEE Trans. Ind. Electron. 59(2): 1278-1287 (2012) - [c68]Shiang-Yu Tsai, Chun-Yu Lin, Li-Wei Chu, Ming-Dou Ker:
Design of ESD protection for RF CMOS power amplifier with inductor in matching network. APCCAS 2012: 467-470 - [c67]Ya-Chun Huang, Ming-Dou Ker, Chun-Yu Lin:
Design of negative high voltage generator for biphasic stimulator with soc integration consideration. BioCAS 2012: 29-32 - [c66]Ming-Dou Ker, Wei-Ling Chen, Chun-Yu Lin:
Live demonstration: Implantable stimulator for epileptic seizure suppression with loading impedance adaptability. BioCAS 2012: 78 - [c65]Li-Wei Chu, Chun-Yu Lin, Shiang-Yu Tsai, Ming-Dou Ker, Ming-Hsiang Song, Chewnpu Jou, Tse-Hua Lu, Jeng-Chou Tseng, Ming-Hsien Tsai, Tsun-Lai Hsu, Ping-Fang Hung, Tzu-Heng Chang:
Compact and low-loss ESD protection design for V-band RF applications in a 65-nm CMOS technology. ISCAS 2012: 2127-2130 - [c64]Ming-Dou Ker, Wan-Yen Lin:
New design of transient-noise detection circuit with SCR device for system-level ESD protection. NEWCAS 2012: 81-84 - [c63]Chun-Yu Lin, Yi-Ju Li, Ming-Dou Ker:
High-voltage-tolerant stimulator with adaptive loading consideration for electronic epilepsy prosthetic SoC in a 0.18-µm CMOS process. NEWCAS 2012: 125-128 - [c62]Chih-Ting Yeh, Ming-Dou Ker:
New design on 2×VDD-tolerant power-rail ESD clamp circuit with low standby leakage in 65nm CMOS process. VLSI-DAT 2012: 1-4 - 2011
- [j52]Ming-Dou Ker, Wen-Yi Chen, Wuu-Trong Shieh, I-Ju Wei:
Electrostatic Discharge Protection Design for High-Voltage Programming Pin in Fully-Silicided CMOS ICs. IEEE J. Solid State Circuits 46(2): 537-545 (2011) - [j51]Yi-Hsin Weng, Hui-Wen Tsai, Ming-Dou Ker:
Design to suppress return-back leakage current of charge pump circuit in low-voltage CMOS process. Microelectron. Reliab. 51(5): 871-878 (2011) - [j50]Chun-Yu Lin, Li-Wei Chu, Ming-Dou Ker:
Design and implementation of configurable ESD protection cell for 60-GHz RF circuits in a 65-nm CMOS process. Microelectron. Reliab. 51(8): 1315-1324 (2011) - [c61]Chun-Yu Lin, Li-Wei Chu, Shiang-Yu Tsai, Ming-Dou Ker, Tse-Hua Lu, Tsun-Lai Hsu, Ping-Fang Hung, Ming-Hsiang Song, Jeng-Chou Tseng, Tzu-Heng Chang, Ming-Hsien Tsai:
Modified LC-tank ESD protection design for 60-GHz RF applications. ECCTD 2011: 57-60 - [c60]Chih-Ting Yeh, Yung-Chih Liang, Ming-Dou Ker:
Design of power-rail ESD clamp circuit with adjustable holding voltage against mis-trigger or transient-induced latch-on events. ISCAS 2011: 1403-1406 - 2010
- [j49]Chih-Ting Yeh, Ming-Dou Ker:
Capacitor-Less Design of Power-Rail ESD Clamp Circuit With Adjustable Holding Voltage for On-Chip ESD Protection. IEEE J. Solid State Circuits 45(11): 2476-2486 (2010) - [j48]Hui-Wen Tsai, Ming-Dou Ker:
Design of 2xVDD-tolerant mixed-voltage I/O buffer against gate-oxide reliability and hot-carrier degradation. Microelectron. Reliab. 50(1): 48-56 (2010) - [j47]Shih-Hung Chen, Ming-Dou Ker:
Investigation on NMOS-based power-rail ESD clamp circuits with gate-driven mechanism in a 0.13-µm CMOS technology. Microelectron. Reliab. 50(6): 821-830 (2010) - [j46]Chun-Yu Lin, Ming-Dou Ker, Yuan-Wen Hsiao:
Design of differential low-noise amplifier with cross-coupled-SCR ESD protection scheme. Microelectron. Reliab. 50(6): 831-838 (2010) - [j45]Wen-Yi Chen, Ming-Dou Ker:
Circuit and Layout Co-Design for ESD Protection in Bipolar-CMOS-DMOS (BCD) High-Voltage Process. IEEE Trans. Circuits Syst. I Regul. Pap. 57-I(5): 1039-1047 (2010) - [j44]Ming-Dou Ker, Cheng-Cheng Yen:
New Transient Detection Circuit for On-Chip Protection Design Against System-Level Electrical-Transient Disturbance. IEEE Trans. Ind. Electron. 57(10): 3533-3543 (2010) - [c59]Ming-Dou Ker, Che-Lun Hsu, Wen-Yi Chen:
ESD protection circuit for high-voltage CMOS ICs with improved immunity against transient-induced latchup. ISCAS 2010: 989-992 - [c58]Chun-Yu Lin, Ming-Dou Ker:
2×VDD-tolerant power-rail ESD clamp circuit with low standby leakage in 65-nm CMOS process. ISCAS 2010: 3417-3420
2000 – 2009
- 2009
- [j43]Ming-Dou Ker, Yuan-Wen Hsiao:
Impedance-Isolation Technique for ESD Protection Design in RF Integrated Circuits. IEICE Trans. Electron. 92-C(3): 341-351 (2009) - [j42]Chang-Tzu Wang, Ming-Dou Ker:
Design of Power-Rail ESD Clamp Circuit With Ultra-Low Standby Leakage Current in Nanoscale CMOS Technology. IEEE J. Solid State Circuits 44(3): 956-964 (2009) - [j41]Yuan-Wen Hsiao, Ming-Dou Ker:
Low-capacitance ESD protection design for high-speed I/O interfaces in a 130-nm CMOS process. Microelectron. Reliab. 49(6): 650-659 (2009) - [j40]Shih-Hung Chen, Ming-Dou Ker:
Area-Efficient ESD-Transient Detection Circuit With Smaller Capacitance for On-Chip Power-Rail ESD Protection in CMOS ICs. IEEE Trans. Circuits Syst. II Express Briefs 56-II(5): 359-363 (2009) - [j39]Tzu-Ming Wang, Ming-Dou Ker, Hung-Tai Liao:
Design of Mixed-Voltage-Tolerant Crystal Oscillator Circuit in Low-Voltage CMOS Technology. IEEE Trans. Circuits Syst. I Regul. Pap. 56-I(5): 966-974 (2009) - [c57]Ming-Dou Ker, Yan-Liang Lin:
Design of 2xVDD-tolerant I/O buffer with 1xVDD CMOS devices. CICC 2009: 539-542 - [c56]Ming-Dou Ker, Chang-Tzu Wang:
Circuit solutions on ESD protection design for mixed-voltage I/O buffers in nanoscale CMOS. CICC 2009: 689-696 - [c55]Wen-Yi Chen, Ming-Dou Ker, Yeh-Ning Jou, Yeh-Jen Huang, Geeng-Lih Lin:
Improvement on ESD Robustness of Lateral DMOS in High-voltage CMOS ICs by Body Current Injection. ISCAS 2009: 385-388 - [c54]Ming-Dou Ker, Po-Yen Chiu, Fu-Yi Tsai, Yeong-Jar Chang:
On the Design of Power-rail ESD Clamp Circuit with Consideration of Gate Leakage Current in 65-nm Low-voltage CMOS Process. ISCAS 2009: 2281-2284 - 2008
- [j38]Jung-Sheng Chen, Ming-Dou Ker:
Circuit Performance Degradation of Switched-Capacitor Circuit with Bootstrapped Technique due to Gate-Oxide Overstress in a 130-nm CMOS Process. IEICE Trans. Electron. 91-C(3): 378-384 (2008) - [j37]Chun-Yu Lin, Ming-Dou Ker, Guo-Xuan Meng:
Low-Capacitance and Fast Turn-on SCR for RF ESD Protection. IEICE Trans. Electron. 91-C(8): 1321-1330 (2008) - [j36]Ming-Dou Ker, Cheng-Cheng Yen:
Investigation and Design of On-Chip Power-Rail ESD Clamp Circuits Without Suffering Latchup-Like Failure During System-Level ESD Test. IEEE J. Solid State Circuits 43(11): 2533-2545 (2008) - [c53]Wen-Yi Chen, Ming-Dou Ker, Yeh-Jen Huang, Yeh-Ning Jou, Geeng-Lih Lin:
Measurement on snapback holding voltage of high-voltage LDMOS for latch-up consideration. APCCAS 2008: 61-64 - [c52]Yuan-Wen Hsiao, Ming-Dou Ker:
An ESD-protected 5-GHz differential low-noise amplifier in a 130-nm CMOS process. CICC 2008: 233-236 - [c51]Ting-Chou Lu, Ming-Dou Ker, Hsiao-Wen Zan, Chun-Hung Kuo, Chun-Huai Li, Yao-Jen Hsieh, Chun-Ting Liu:
Design of bandgap voltage reference circuit with all TFT devices on glass substrate in a 3-μm LTPS process. CICC 2008: 721-724 - [c50]Tzu-Ming Wang, Yu-Hsuan Li, Ming-Dou Ker:
On-glass digital-to-analog converter with gamma correction for panel data driver. ICECS 2008: 202-205 - [c49]Shih-Hung Chen, Ming-Dou Ker:
Optimization on NMOS-based power-rail ESD clamp circuits with gate-driven mechanism in a 0.13-μm CMOS technology. ICECS 2008: 666-669 - [c48]Ming-Dou Ker, Tzu-Ming Wang, Fang-Ling Hu:
Design on mixed-voltage I/O buffers with slew-rate control in low-voltage CMOS process. ICECS 2008: 1047-1050 - [c47]Ming-Dou Ker, Tzu-Ming Wang, Hung-Tai Liao:
2xVDD-tolerant crystal oscillator circuit realized with 1xVDD CMOS devices without gate-oxide reliability issue. ISCAS 2008: 820-823 - [c46]Ming-Dou Ker, Chun-Yu Lin, Guo-Xuan Meng:
ESD protection design for fully integrated CMOS RF power amplifiers with waffle-structured SCR. ISCAS 2008: 1292-1295 - 2007
- [j35]Ming-Dou Ker, Shih-Hung Chen:
Implementation of Initial-On ESD Protection Concept With PMOS-Triggered SCR Devices in Deep-Submicron CMOS Technology. IEEE J. Solid State Circuits 42(5): 1158-1168 (2007) - [j34]Ming-Dou Ker, Wei-Jen Chang:
Overview on ESD protection design for mixed-voltage I/O interfaces with high-voltage-tolerant power-rail ESD clamp circuits in low-voltage thin-oxide CMOS technology. Microelectron. Reliab. 47(1): 27-35 (2007) - [j33]Shih-Hung Chen, Ming-Dou Ker:
Active ESD protection circuit design against charged-device-model ESD event in CMOS integrated circuits. Microelectron. Reliab. 47(9-11): 1502-1505 (2007) - [j32]Shih-Lun Chen, Ming-Dou Ker:
An Output Buffer for 3.3-V Applications in a 0.13- μħbox m 1/2.5-V CMOS Process. IEEE Trans. Circuits Syst. II Express Briefs 54-II(1): 14-18 (2007) - [j31]Ming-Dou Ker, Shih-Lun Chen:
Ultra-High-Voltage Charge Pump Circuit in Low-Voltage Bulk CMOS Processes With Polysilicon Diodes. IEEE Trans. Circuits Syst. II Express Briefs 54-II(1): 47-51 (2007) - [c45]Tzu-Ming Wang, Wan-Yi Shen, Ming-Dou Ker:
A New Architecture for Charge Pump Circuit Without Suffering Gate-Oxide Reliability in Low-Voltage CMOS Processes. ICECS 2007: 206-209 - [c44]Yu-Da Shiu, Bo-Shih Huang, Ming-Dou Ker:
CMOS Power Amplifier with ESD Protection Design Merged in Matching Network. ICECS 2007: 825-828 - [c43]Hui-Wen Tsai, Ming-Dou Ker:
Design of 2�?VDD-Tolerant I/O Buffer with Considerations of Gate-Oxide Reliability and Hot-Carrier Degradation. ICECS 2007: 1240-1243 - [c42]Ming-Dou Ker, Hung-Tai Liao:
Design of Mixed-Voltage Crystal Oscillator Circuit in Low-Voltage CMOS Technology. ISCAS 2007: 1121-1124 - [c41]Yuan-Wen Hsiao, Ming-Dou Ker, Po-Yen Chiu, Chun Huang, Yuh-Kuang Tseng:
ESD protection design for Giga-Hz high-speed I/O interfaces in a 130-nm CMOS process. SoCC 2007: 277-280 - 2006
- [j30]Ming-Dou Ker, Shih-Lun Chen, Chia-Sheng Tsai:
Design of charge pump circuit with consideration of gate-oxide reliability in low-voltage CMOS processes. IEEE J. Solid State Circuits 41(5): 1100-1107 (2006) - [j29]Ming-Dou Ker, Shih-Lun Chen:
Design of Mixed-Voltage I/O Buffer by Using NMOS-Blocking Technique. IEEE J. Solid State Circuits 41(10): 2324-2333 (2006) - [j28]Ming-Dou Ker, Jia-Huei Chen:
Self-Substrate-Triggered Technique to Enhance Turn-On Uniformity of Multi-Finger ESD Protection Devices. IEEE J. Solid State Circuits 41(11): 2601-2609 (2006) - [j27]Kun-Hsien Lin, Ming-Dou Ker:
Electrostatic discharge protection scheme without leakage current path for CMOS IC operating in power-down-mode condition on a system board. Microelectron. Reliab. 46(2-4): 301-310 (2006) - [j26]Shih-Hung Chen, Ming-Dou Ker:
Failure analysis and solutions to overcome latchup failure event of a power controller IC in bulk CMOS technology. Microelectron. Reliab. 46(7): 1042-1049 (2006) - [j25]Chih-Kang Deng, Ming-Dou Ker:
ESD robustness of thin-film devices with different layout structures in LTPS technology. Microelectron. Reliab. 46(12): 2067-2073 (2006) - [j24]Ming-Dou Ker, Kun-Hsien Lin:
Overview on electrostatic discharge protection designs for mixed-voltage I/O interfaces: design concept and circuit implementations. IEEE Trans. Circuits Syst. I Regul. Pap. 53-I(2): 235-246 (2006) - [j23]Ming-Dou Ker, Jung-Sheng Chen:
New Curvature-Compensation Technique for CMOS Bandgap Reference With Sub-1-V Operation. IEEE Trans. Circuits Syst. II Express Briefs 53-II(8): 667-671 (2006) - [j22]