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ORCIDISPD 2000: San Diego, CA, USA
- Manfred Wiesel, Dwight D. Hill:
Proceedings of the 2000 International Symposium on Physical Design, ISPD 2000, San Diego, CA, USA, April 9-12, 2000. ACM 2000, ISBN 1-58113-191-7 - Andrew B. Kahng, Stefanus Mantik, Dirk Stroobandt:
Requirements for models of achievable routing. 4-11 - Jason Cong, Jie Fang, Kei-Yong Khoo:
DUNE: a multi-layer gridless routing system with wire planning. 12-18 - Christoph Albrecht:
Provably good global routing by a new approximation algorithm for multicommodity flow. 19-25 - Frank Schmiedle, Daniel Unruh, Bernd Becker
:
Exact switchbox routing with search space reduction. 26-32 - I-Min Liu, Tan-Li Chou, Adnan Aziz, D. F. Wong:
Zero-skew clock tree construction by simultaneous routing, wire sizing and buffer insertion. 33-38 - Naveed A. Sherwani:
The bottom-10 problems in EDA (panel session (title only)). 39 - Chin-Chih Chang, Jason Cong:
Pseudo pin assignment with crosstalk noise control. 41-47 - Lauren Hui Chen, Malgorzata Marek-Sadowska:
Aggressor alignment for worst-case coupling noise. 48-54 - Lei He, Kevin M. Lepak:
Simultaneous shield insertion and net ordering for capacitive and inductive coupling minimization. 55-60 - Rony Kay, Rob A. Rutenbar:
Wire packing: a strong formulation of crosstalk-aware chip-level track/layer assignment with an efficient integer programming solution. 61-68 - Charles J. Alpert, Anirudh Devgan, Chandramouli V. Kashyap:
A two moment RC delay metric for performance optimization. 69-74 - Rob A. Rutenbar, John M. Cohn:
Layout tools for analog ICs and mixed-signal SoCs: a survey. 76-83 - Jason Cong, Majid Sarrafzadeh:
Incremental physical design. 84-92 - Utpal Desai, Simon M. Tam, Robert Kim, Ji Zhang, Stefan Rusu:
Itanium processor clock design. 94-98 - Rory McInerney, Kurt Leeper, Troy Hill, Heming Chan, Bülent Basaran, Lance McQuiddy:
Methodology for repeater insertion management in the RTL, layout, floorplan and fullchip timing databases of the Itanium microprocessor. 99-104 - Hai Zhou, Adnan Aziz:
Buffer minimization in pass transistor logic. 105-110 - Masanori Hashimoto, Hidetoshi Onodera:
A performance optimization method by gate sizing using statistical static timing analysis. 111-116 - Li-Fu Chang, Keh-Jeng Chang, Robert Mathews:
Simulating frequency-dependent current distribution for inductance modeling of on-chip copper interconnects. 117-120 - Suresh Raman, Sachin S. Sapatnekar, Charles J. Alpert:
Datapath routing based on a decongestion metric. 122-127 - Iris Hui-Ru Jiang, Song-Ra Pan, Yao-Wen Chang, Jing-Yang Jou:
Optimal reliable crosstalk-driven interconnect optimization. 128-133 - Yu-Yen Mo, Chris C. N. Chu:
A hybrid dynamic/quadratic programming algorithm for interconnect tree optimization. 134-139 - Evanthia Papadopoulou:
Critical area computation for missing material defects in VLSI circuits. 140-146 - Maogang Wang, Xiaojian Yang, Kenneth Eguro, Majid Sarrafzadeh:
Multi-center congestion estimation and minimization during placement. 147-152 - Xiaojian Yang, Maogang Wang, Kenneth Eguro, Majid Sarrafzadeh:
A snap-on placement tool. 153-158 - Masahiko Toyonaga, Keiichi Kurokawa, Takuya Yasui, Atsushi Takahashi:
A practical clock tree synthesis for semi-synchronous circuits. 159-164 - D. Hill, Mark Gilbreath, Wayne Heideman, J. George Janac, Adriaan Ligtenberg:
EDA and the Internet (panel session - title only). 165 - Yingxin Pang, Chung-Kuan Cheng, Takeshi Yoshimura:
An enhanced perturbing algorithm for floorplan design using the O-tree representation. 168-173 - Fung Yu Young, Chris C. N. Chu, W. S. Luk, Y. C. Wong:
Floorplan area minimization using Lagrangian relaxation. 174-179 - Xiaoping Tang, D. F. Wong:
Planning buffer locations by network flows. 180-185 - Probir Sarkar, Vivek Sundararaman, Cheng-Kok Koh:
Routability-driven repeater block planning for interconnect-centric floorplanning. 186-191 - Min Ouyang, Michel Toulouse, Krishnaiyan Thulasiraman, Fred W. Glover, Jitender S. Deogun:
Multilevel cooperative search: application to the circuit/hypergraph partitioning problem. 192-198 - Ralph H. J. M. Otten:
What is a floorplan?. 201-206 - Andrew B. Kahng:
Classical floorplanning harmful? 207-213 - Patrick Groeneveld, Jacob Greidinger, J. George Janac, Wilm E. Donath:
The right floorplanning formulations for future chip implementation methodologies (panel discussion - title only). 214
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