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ORCIDISPD 2006: San Jose, California, USA
- Louis Scheffer:
Proceedings of the 2006 International Symposium on Physical Design, ISPD 2006, San Jose, California, USA, April 9-12, 2006. ACM 2006, ISBN 1-59593-299-2 - Ted Vucurevich:
Commercial CAD: challenges and opportunities. 1
Timing and variability
- Jinjun Xiong
, Vladimir Zolotov, Lei He:
Robust extraction of spatial correlation. 2-9 - B. Lasbouygues, Robin Wilson, Nadine Azémard, Philippe Maurine:
Timing analysis in presence of supply voltage and temperature variations. 10-16 - Azadeh Davoodi, Ankur Srivastava:
Probabilistic evaluation of solutions in variability-driven optimization. 17-24 - Yiyu Shi, Hao Yu, Lei He:
SAMSON: a generalized second-order arnoldi method for reducing multiple source linear network with susceptance. 25-32 - Lizheng Zhang, Jun Shao, Charlie Chung-Ping Chen:
Non-gaussian statistical parameter modeling for SSTA with confidence interval analysis. 33-38
Failure is not an option
- Jens Lienig:
introduction to electromigration-aware physical design. 39-46 - Anne E. Gattiker:
IC failure mechanisms yesterday, today, tomorrow: implications from test to DFM. 47
Routing
- Zhe Feng, Yu Hu, Tong Jing, Xianlong Hong, Xiaodong Hu, Guiying Yan:
An O(nlogn) algorithm for obstacle-avoiding routing tree construction in the lambda-geometry plane. 48-55 - Bor-Yiing Su, Yao-Wen Chang, Jiang Hu:
An optimal jumper insertion algorithm for antenna avoidance/fixing on general routing trees with obstacles. 56-63 - Hsin-Yu Chen, Zhi-Da Lin:
NEMO: a new implicit connection graph-based gridless router with multi-layer planes and pseudo-tile propagation. 64-71 - Mehdi Saeedi, Morteza Saheb Zamani, Ali Jahanian:
Prediction and reduction of routing congestion. 72-77 - Jarrod A. Roy, James F. Lu, Igor L. Markov:
Seeing the forest and the trees: Steiner wirelength optimization in placemen. 78-85
Power and noise
- Chen-Wei Liu, Yao-Wen Chang:
Floorplan and power/ground network co-synthesis for fast design convergence. 86-93 - Jun Chen, Lei He:
Noise driven in-package decoupling capacitor optimization for power integrity. 94-101 - Andrew B. Kahng, Bao Liu, Sheldon X.-D. Tan:
Efficient decoupling capacitor planning via convex programming methods. 102-107 - Jin Shi, Yici Cai, Sheldon X.-D. Tan, Xianlong Hong:
High accurate pattern based precondition method for extremely large power/ground grid analysis. 108-113 - Shanq-Jang Ruan, Edwin Naroska, Chun-Chih Chen:
Optimal partitioned fault-tolerant bus layout for reducing power in nanometer designs. 114-119
Optimized interconnect
- Christoph Bartoschek, Stephan Held, Dieter Rautenbach, Jens Vygen:
Efficient generation of short and fast repeater tree topologies. 120-127 - Jinjun Xiong, Lei He:
Fast buffer insertion considering process variations. 128-135 - Beth L. Chen, Dmitri B. Chklovskii:
Placement and routing optimization in the brain. 136-141
Chip-level timing and wiring
- Mongkol Ekpanyapong, Sung Kyu Lim:
Integrated retiming and simultaneous Vdd/Vth scaling for total power minimization. 142-148 - Uday Padmanabhan, Janet Meiling Wang, Jiang Hu:
Statistical clock tree routing for robustness to process variations. 149-156 - Anand Rajaram, David Z. Pan:
Variation tolerant buffered clock network synthesis with cross links. 157-164
Big designs and the ISPD06 placement contest
- P. V. Srinivas:
Chip assembly: a new paradigm in hierarchical physical design. 165 - François Rémond:
Physical design challenges for multi-million gate SoC's: an STMicroelectronics perspective. 166 - Gi-Joon Nam:
ISPD 2006 Placement Contest: Benchmark Suite and Results. 167
Industrial clocking
- Arjun Rajagopal:
Clock tree design challenges for robust and low power design. 168 - Ad M. G. Peeters:
Clockless IC design using handshake technology. 169
Placement
- Aaron N. Ng, Igor L. Markov, Rajat Aggarwal, Venky Ramachandran:
Solving hard instances of floorplacement. 170-177 - Zhuoyuan Li, Xianlong Hong, Qiang Zhou, Shan Zeng, Jinian Bian, Hannah Honghua Yang, Vijay Pitchumani, Chung-Kuan Cheng:
Integrating dynamic thermal via planning with 3D floorplanning algorithm. 178-185 - Sherief Reda, Amit Chowdhary:
Effective linear programming based placement methods. 186-191 - Shinichi Kouda, Chikaaki Kodama, Kunihiro Fujiyoshi:
Improved method of cell placement with symmetry constraints for analog IC layout design. 192-199 - Jianhua Li, Laleh Behjat:
Net cluster: a net-reduction based clustering preprocessing algorithm. 200-205
Placement contest papers
- Jarrod A. Roy, David A. Papa, Aaron N. Ng, Igor L. Markov:
Satisfying whitespace requirements in top-down placement. 206-208 - Taraneh Taghavi, Xiaojian Yang, Bo-Kyung Choi, Maogang Wang, Majid Sarrafzadeh:
Dragon2006: blockage-aware congestion-controlling mixed-size placer. 209-211 - Tony F. Chan, Jason Cong, Joseph R. Shinnerl, Kenton Sze, Min Xie:
mPL6: enhanced multilevel mixed-size placement. 212-214 - Zhe-Wei Jiang, Tung-Chieh Chen, Tien-Chang Hsu, Hsin-Chen Chen, Yao-Wen Chang:
NTUplace2: a hybrid placer using partitioning and analytical techniques. 215-217 - Andrew B. Kahng, Qinke Wang:
A faster implementation of APlace. 218-220
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