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ORCIDAnanta K. Majhi
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2010 – 2019
- 2012
[j5]Elif Alpaslan, Bram Kruseman, Ananta K. Majhi, Wilmar M. Heuvelman, Jennifer Dworak:
NIM-X: A Noise Index Model-Based X-Filling Technique to Overcome the Power Supply Switching Noise Effects on Path Delay Test. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(5): 809-813 (2012)- 2010
- [c21]Elif Alpaslan, Jennifer Dworak, Bram Kruseman, Ananta K. Majhi, Wilmar M. Heuvelman, Paul van de Wiel:
NIM- a noise index model to estimate delay discrepancies between silicon and simulation. DATE 2010: 1373-1376 - [c20]Lavanya Jagan, Camelia Hora, Bram Kruseman, Stefan Eichenberger, Ananta K. Majhi, V. Kamakoti:
Impact of Temperature on Test Quality. VLSI Design 2010: 276-281
2000 – 2009
- 2009
- [c19]Lavanya Jagan, Ratan Deep Singh, V. Kamakoti, Ananta K. Majhi:
Efficient Grouping of Fail Chips for Volume Yield Diagnostics. VLSI Design 2009: 97-102 - 2008
- [c18]Stefan Eichenberger, Jeroen Geuzebroek, Camelia Hora, Bram Kruseman, Ananta K. Majhi:
Towards a World Without Test Escapes: The Use of Volume Diagnosis to Improve Test Quality. ITC 2008: 1-10 - 2007
- [j4]Jing Wang, Duncan M. Hank Walker, Xiang Lu, Ananta K. Majhi, Bram Kruseman, Guido Gronthoud, Luis Elvira Villagra, Paul J. A. M. van de Wiel, Stefan Eichenberger:
Modeling Power Supply Noise in Delay Testing. IEEE Des. Test Comput. 24(3): 226-234 (2007) - [c17]Jeroen Geuzebroek, Erik Jan Marinissen
, Ananta K. Majhi, Andreas Glowatz, Friedrich Hapke:
Embedded multi-detect ATPG and Its Effect on the Detection of Unmodeled Defects. ITC 2007: 1-10 - [c16]Bram Kruseman, Ananta K. Majhi, Guido Gronthoud:
On Performance Testing with Path Delay Patterns. VTS 2007: 29-34 - [c15]Daniel Arumí, Rosa Rodríguez-Montañés, Joan Figueras, Stefan Eichenberger, Camelia Hora, Bram Kruseman, Maurice Lousberg, Ananta K. Majhi:
Diagnosis of Bridging Defects Based on Current Signatures at Low Power Supply Voltages. VTS 2007: 145-150 - [c14]Rosa Rodríguez-Montañés, Daniel Arumí, Joan Figueras, Stefan Eichenberger, Camelia Hora, Bram Kruseman, Maurice Lousberg, Ananta K. Majhi:
Diagnosis of Full Open Defects in Interconnecting Lines. VTS 2007: 158-166 - [i1]Ananta K. Majhi, Mohamed Azimane, Guido Gronthoud, Maurice Lousberg, Stefan Eichenberger, Fred Bowen:
Memory Testing Under Different Stress Conditions: An Industrial Evaluation. CoRR abs/0710.4693 (2007) - 2006
- [c13]Jing Wang, D. M. H. Walker, Ananta K. Majhi, Bram Kruseman, Guido Gronthoud, Luis Elvira Villagra, Paul van de Wiel, Stefan Eichenberger:
Power Supply Noise in Delay Testing. ITC 2006: 1-10 - 2005
- [c12]Ananta K. Majhi, Mohamed Azimane, Guido Gronthoud, Maurice Lousberg, Stefan Eichenberger, Fred Bowen:
Memory Testing Under Different Stress Conditions: An Industrial Evaluation. DATE 2005: 438-443 - [c11]Ananta K. Majhi, Mohamed Azimane, Guido Gronthoud, Maurice Lousberg, Stefan Eichenberger, Fred Bowen:
Memory testing improvements through different stress conditions. ESSCIRC 2005: 299-302 - [c10]Mohamed Azimane, Ananta K. Majhi, Guido Gronthoud, Maurice Lousberg:
A New Algorithm for Dynamic Faults Detection in RAMs. VTS 2005: 177-182 - 2004
- [c9]Bram Kruseman, Ananta K. Majhi, Guido Gronthoud, Stefan Eichenberger:
On Hazard-free Patterns for Fine-delay Fault Testing. ITC 2004: 213-222 - [c8]Bram Kruseman, Ananta K. Majhi, Camelia Hora, Stefan Eichenberger, Johan Meirlevede:
Systematic Defects in Deep Sub-Micron Technologies. ITC 2004: 290-299 - [c7]Mohamed Azimane, Ananta K. Majhi:
New Test Methodology for Resistive Open Defect Detection in Memory Address Decoders. VTS 2004: 123-128 - 2003
- [c6]Ananta K. Majhi, Guido Gronthoud, Camelia Hora, Maurice Lousberg, Pop Valer, Stefan Eichenberger:
Improving Diagnostic Resolution of Delay Faults using Path Delay Fault Model. VTS 2003: 345-350 - 2000
- [j3]Ananta K. Majhi, V. D. Agrawak, James Jacob, Lalit M. Patnaik:
Line coverage of path delay faults. IEEE Trans. Very Large Scale Integr. Syst. 8(5): 610-614 (2000)
1990 – 1999
- 1998
- [c5]Ananta K. Majhi, Vishwani D. Agrawal:
Mixed-Signal Test. VLSI Design 1998: 285-288 - [c4]Ananta K. Majhi, Vishwani D. Agrawal:
Tutorial: Delay Fault Models and Coverage. VLSI Design 1998: 364-369 - [c3]S. Balajee, Ananta K. Majhi:
Automated AC (Timing) Characterization for Digital Circuit Testing. VLSI Design 1998: 374-377 - 1996
- [j2]Ananta K. Majhi, James Jacob, Lalit M. Patnaik:
A Novel Path Delay Fault Simulator Using Binary Logic. VLSI Design 4(3): 167-179 (1996) - [c2]Ananta K. Majhi, James Jacob, Lalit M. Patnaik, Vishwani D. Agrawal:
On test coverage of path delay faults. VLSI Design 1996: 418-421 - 1995
- [j1]Ananta K. Majhi, Lalit M. Patnaik, Srilata Raman:
A genetic algorithm-based circuit partitioner for MCMs. Microprocess. Microprogramming 41(1): 83-96 (1995) - [c1]Ananta K. Majhi, James Jacob, Lalit M. Patnaik, Vishwani D. Agrawal:
An efficient automatic test generation system for path delay faults in combinational circuits. VLSI Design 1995: 161-165
Coauthor Index
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