default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCID23rd VLSI Design 2010: Bangalore, India
- VLSI Design 2010: 23rd International Conference on VLSI Design, 9th International Conference on Embedded Systems, Bangalore, India, 3-7 January 2010. IEEE Computer Society 2010, ISBN 978-0-7695-3928-7
- Irith Pomeranz, Sudhakar M. Reddy:
Output-Dependent Diagnostic Test Generation. 3-8 - Zhen Chen, Sharad C. Seth, Dong Xiang, Bhargab B. Bhattacharya:
A Unified Solution to Scan Test Volume, Time, and Power Minimization. 9-14 - Gautam Hazari, Madhav P. Desai, G. Srinivas:
Bottleneck Identification Techniques Leading to Simplified Performance Models for Efficient Design Space Exploration in VLSI Memory Systems. 15-20 - Sudipta Sarkar, Ananda S. Roy, Santanu Mahapatra:
A Non Quasi-static Small Signal Model for Long Channel Symmetric DG MOSFET. 21-26 - J. Manikandan
, B. Venkataramani, M. Bhaskar, K. Ashish, R. Raghul, V. Mathangi:
Implementation of a Novel Phoneme Recognition System Using TMS320C6713 DSP. 27-32 - Usha Sandeep Mehta, Kankar S. Dasgupta, Nirnjan M. Devashrayee:
Hamming Distance Based Reordering and Columnwise Bit Stuffing with Difference Vector: A Better Scheme for Test Data Compression with Run Length Based Codes. 33-38 - Irith Pomeranz, Sudhakar M. Reddy:
Identifying Tests for Logic Fault Models Involving Subsets of Lines without Fault Enumeration. 39-44 - Garima Thakral, Saraju P. Mohanty, Dhruva Ghai, Dhiraj K. Pradhan:
A Combined DOE-ILP Based Power and Read Stability Optimization in Nano-CMOS SRAM. 45-50 - Hao Xu, Wen-Ben Jone, Ranga Vemuri:
Novel Vth Hopping Techniques for Aggressive Runtime Leakage Control. 51-56 - Mohammad Arjomand, Hamid Sarbazi-Azad:
Voltage-Frequency Planning for Thermal-Aware, Low-Power Design of Regular 3-D NoCs. 57-62 - Ming Xu, Gary Gréwal:
A Graph-Based I/O Pad Pre-placement Technique for Use with Analytic FPGA Placement Methods. 63-68 - Yang Zhao, Ryan Sturmer, Krishnendu Chakrabarty, Vamsee K. Pamula:
Synchronization of Concurrently-Implemented Fluidic Operations in Pin-Constrained Digital Microfluidic Biochips. 69-74 - Shashank Prasad, Dongzi Liu, Oleg Levitsky, Dave Noice, Shailendra Srivastava:
Post Assembly Timing Closure for Multi Million Gate Chips. 75-80 - Ansuman Banerjee:
Synthesizability of 3 Party Formal Specifications-Does My Controller See Enough?. 81-86 - Rohan Mandrekar, Yaping Zhou, Sungjun Chun, Anand Haridass, Jinwoo Choi, Nanju Na, Daniel M. Dreps, Roger D. Weekly, Paul Harvey:
Channel Optimization for the Design of High Speed I/O links. 87-92 - Irina Hashmi, Hafiz Md. Hasan Babu:
An Efficient Design of a Reversible Barrel Shifter. 93-98 - Saraju P. Mohanty, Dhruva Ghai, Elias Kougianos:
A P4VT (Power Performance Process Parasitic Voltage Temperature) Aware Dual-VTh Nano-CMOS VCO. 99-104 - Debasri Saha, Susmita Sur-Kolay:
A Unified Approach for IP Protection across Design Phases in a Packaged Chip. 105-110 - Vaidyanathan Subramanian, Abdelkarim Mercha, Bertrand Parvais, Morin Dehan, Guido Groeseneken, Willy M. C. Sansen, Stefaan Decoutere:
Identifying the Bottlenecks to the RF Performance of FinFETs. 111-116 - Sanjeev K. Jain, Krishna Srivastva, Sanjiv Kainth:
A Novel Circuit to Optimize Access Time and Decoding Schemes in Memories. 117-121 - Syed Saif Abrar, Aravinda Thimmapuram:
Functional Refinement: A Generic Methodology for Managing ESL Abstractions. 122-127 - Arnab Sarkar, Rahul Nanda, Sujoy Ghose, P. P. Chakrabarti:
Safe-ERfair. 128-133 - Alpesh Patel, Hemangee K. Kapoor:
Exploring Use of NoC for Reconfigurable Video Coding. 134-139 - Aritra Hazra, Priyankar Ghosh, Pallab Dasgupta, Partha Pratim Chakrabarti:
Coverage Management with Inline Assertions and Formal Test Points. 140-145 - Nidhi Arora, Kiran Chandramohan, Nagaraju Pothineni, Anshul Kumar:
Instruction Selection in ASIP Synthesis Using Functional Matching. 146-151 - Ramen Dutta, Tarun Kanti Bhattacharyya, Xiang Gao, Eric A. M. Klumperink:
Optimized Stage Ratio of Tapered CMOS Inverters for Minimum Power and Mismatch Jitter Product. 152-157 - Bharghava Rajaram, Abinesh Ramachandran, Suresh Purini, Govindarajulu Regeti:
Inexact Decision Circuits: An Application to Hamming Weight Threshold Voting. 158-163 - Abinesh Ramachandran, Bharghava Rajaram, Suresh Purini, Govindarajulu Regeti:
Transition Inversion Based Low Power Data Coding Scheme for Buffered Data Transfer. 164-169 - Ambarish Roy, Bradley P. Barber, Kanti Prasad:
Modeling of RF- MEMS BAW Resonator. 170-175 - Arijit Mondal, Partha Pratim Chakrabarti, Pallab Dasgupta:
Accelerating Synchronous Sequential Circuits Using an Adaptive Clock. 176-181 - Kalyan Bhattacharyya:
23.97GHz CMOS Distributed Voltage Controlled Oscillators with Inverter Gain Cells and Frequency Tuning by Body Bias and MOS Varactors Concurrently. 182-187 - Shyam Parthasarathy, Balaji Swaminathan, Ananth Sundaram, Robert A. Groves:
Design Considerations for BEOL MIM Capacitor Modeling in RF CMOS Processes. 188-193 - Shyam Parthasarathy, Amit Ranjan Trivedi, Saurabh Sirohi, Robert A. Groves, Michael Olsen, Yogesh Singh Chauhan, Michael Carroll, Dan Kerr, Ali Tombak, Phil Mason:
RF SOI Switch FET Design and Modeling Tradeoffs for GSM Applications. 194-199 - Glenn Leary, Karam S. Chatha:
Design of NoC for SoC with Multiple Use Cases Requiring Guaranteed Performance. 200-205 - Zichu Qi, Qi Guo, Ge Zhang, Xiangku Li, Weiwu Hu:
Design of Low-Cost High-Performance Floating-Point Fused Multiply-Add with Reduced Power. 206-211 - Muthubalan Varadharajaperumal, Saurabh Sirohi, Sourabh Khandelwal, Ethirajan Tamilmani, Vaidyananthan Subramanian:
Modeling of High Frequency Noise in SOI MOSFETs. 212-217 - Vinayak Honkote, Baris Taskin:
Analysis, Design and Simulation of Capacitive Load Balanced Rotary Oscillatory Array. 218-223 - Tuck-Boon Chan, Puneet Gupta:
On Electrical Modeling of Imperfect Diffusion Patterning. 224-229 - Radhakrishnan Sithanandam, Mamidala Jagadesh Kumar:
A New Hetero-material Stepped Gate (HSG) SOI LDMOS for RF Power Amplifier Applications. 230-234 - Himanshu Thapliyal, Nagarajan Ranganathan:
Design of Reversible Latches Optimized for Quantum Cost, Delay and Garbage Outputs. 235-240 - Debapriya Sahu, Saravana Ganeshan, Ashish Lachhwani, Rittu Sachdev, B. G. Chandrashekar:
An L-band Fractional-N Synthesizer with Noise-Less Active Capacitor Scaling. 241-245 - Navin K. Ramamoorthy, Jayabharath Reddy M, Vishwanath Muniyappa:
High Speed Serial Link Transmitter for 10Gig Ethernet Applications. 246-251 - Shailendra Jain, Vasantha Erraguntla, Sriram R. Vangal, Yatin Vasant Hoskote, Nitin Borkar, Tulasi Mandepudi, V. P. Karthik:
A 90mW/GFlop 3.4GHz Reconfigurable Fused/Continuous Multiply-Accumulator for Floating-Point and Integer Operands in 65nm. 252-257 - Amit Pande, Joseph Zambreno:
A Reconfigurable Architecture for Secure Multimedia Delivery. 258-263 - Nikhil Gupta, Suman Kalyan Mandal, Javier Malave, Ayan Mandal, Rabi N. Mahapatra:
A Hardware Scheduler for Real Time Multiprocessor System on Chip. 264-269 - Leneesh Raghavan, Ting Wu:
Architectural Comparison of Analog and Digital Duty Cycle Corrector for High Speed I/O Link. 270-275 - Lavanya Jagan, Camelia Hora, Bram Kruseman, Stefan Eichenberger, Ananta K. Majhi, V. Kamakoti:
Impact of Temperature on Test Quality. 276-281 - Sumit Ahuja, Wei Zhang, Avinash Lakshminarayana, Sandeep K. Shukla:
A Methodology for Power Aware High-Level Synthesis of Co-processors from Software Algorithms. 282-287 - Suraj Sindia, Virendra Singh, Vishwani D. Agrawal:
Parametric Fault Diagnosis of Nonlinear Analog Circuits Using Polynomial Coefficients. 288-293 - Samiran DasGupta, Pradip Mandal:
An Improvised MOS Transistor Model Suitable for Geometric Program Based Analog Circuit Sizing in Sub-micron Technology. 294-299 - Kunal Desai, Rajasekhar Nagulapalli, Vijay Krishna, Rajkumar Palwai, Pravin Kumar Venkatesan, Vijay Khawshe:
High Speed Clock and Data Recovery Circuit with Novel Jitter Reduction Technique. 300-305 - Chester Rebeiro, Mainack Mondal, Debdeep Mukhopadhyay:
Pinpointing Cache Timing Attacks on AES. 306-311 - Arunkumar Salimath, Chandrajit Debnath, Kallol Chatterjee, Sushanta K. Mandal:
A 6 bit 800MHz TIADC Based on Successive Approximation in 65nm Standard CMOS Process. 312-317 - Karthick Parashar, Romuald Rocher, Daniel Ménard, Olivier Sentieys:
A Hierarchical Methodology for Word-Length Optimization of Signal Processing Systems. 318-323 - Tamal Das, Pradip Mandal:
On-Chip Inductor-Less DC-DC Boost Converter with Non-overlapped Rotational-Interleaving Scheme. 324-329 - Biju Viswanathan, Vijay Viswam, R. Kulanthaivelu, Joseph J. Vettickatt, S. R. Ramya Nair, Lekshmi S. Chandran:
4 GHz 130nm Low Voltage PLL Based on Self Biased Technique. 330-334 - Balaji Srinivasan, Vinay Bhaskar Chandratre:
An Improved High Resolution CMOS Timing Generator Using Array of Digital Delay Lock Loops. 335-338 - Rajeswari Devadoss, Kolin Paul, M. Balakrishnan:
Clocking-Based Coplanar Wire Crossing Scheme for QCA. 339-344 - Shehzad Hasan, Ajoy Kumar Palit, Walter Anheier:
Test Pattern Generation and Compaction for Crosstalk Induced Glitches and Delay Faults. 345-350 - Xiaoke Qin, Mingsong Chen, Prabhat Mishra:
Synchronized Generation of Directed Tests Using Satisfiability Solving. 351-356 - Weixun Wang, Prabhat Mishra:
Leakage-Aware Energy Minimization Using Dynamic Voltage Scaling and Cache Reconfiguration in Real-Time Systems. 357-362 - Srikanth Pam, Anirban Krishna Bhattacharya, Siddhartha Mukhopadhyay:
An Efficient Method for Bottom-Up Extraction of Analog Behavioral Model Parameters. 363-368 - Amlan Ghosh, Rob Franklin, Richard B. Brown:
Analog Circuit Design Methodologies to Improve Negative-Bias Temperature Instability Degradation. 369-374 - Koushik Chakraborty, Sanghamitra Roy:
Rethinking Threshold Voltage Assignment in 3D Multicore Designs. 375-380 - Ritochit Chakraborty, Arun V. Sathanur, Vikram Jandhyala:
Towards Active-Passive Co-synthesis of Multi-gigaHertz Radio Frequency Circuits. 381-386 - Rance Rodrigues, Sandip Kundu:
Optical Lithography Simulation with Focus Variation using Wavelet Transform. 387-392 - Raghavendra Adiga, Gandhi Arpit, Virendra Singh, Kewal K. Saluja, Hideo Fujiwara, Adit D. Singh:
On Minimization of Test Application Time for RAS. 393-398 - Vinay Saripalli, Vijaykrishnan Narayanan, Suman Datta:
Analyzing Energy-Delay Behavior in Room Temperature Single Electron Transistors. 399-404 - Rajat Subhra Chakraborty, Swarup Bhunia:
RTL Hardware IP Protection Using Key-Based Control and Data Flow Obfuscation. 405-410 - Sandeep Saini, Mahesh Kumar Adimulam, Sreehari Veeramachaneni, M. B. Srinivas:
An Alternative approach to Buffer Insertion for Delay and Power Reduction in VLSI Interconnects. 411-416 - Anshul Kumar, Preeti Ranjan Panda:
Front-End Design Flows for Systems on Chip: An Embedded Tutorial. 417-422 - Tuck-Boon Chan, Rani S. Ghaida, Puneet Gupta:
Electrical Modeling of Lithographic Imperfections. 423-428 - Ruchir Puri, David S. Kung:
The Dawn of 22nm Era: Design and CAD Challenges. 429-433 - Subhasish Mitra:
Robust System Design. 434-439 - Rajiv V. Joshi, Keunwoo Kim, Rouwaida Kanj:
FinFET SRAM Design. 440-445 - Yuan Xie:
Processor Architecture Design Using 3D Integration Technology. 446-451 - Krishnendu Chakrabarty:
Digital Microfluidic Biochips: A Vision for Functional Diversity and More than Moore. 452-457 - Ajit Venkat Rao:
Video Coding Tools and Their Impact on Compression Engine Architecture. 458-463 - Kaushik Roy, Byunghoo Jung, Anand Raghunathan:
Integrated Systems in the More-than-Moore Era: Designing Low-Cost Energy-Efficient Systems Using Heterogeneous Components. 464-469
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2025-12-04 01:25 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
