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ORCIDIEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume 8
Volume 8, Number 1, February 2000
- Yanbing Li, Miriam Leeser
:
HML, a novel hardware description language and its translation to VHDL. 1-8 - Farzan Fallah, Stan Y. Liao, Srinivas Devadas:
Solving covering problems using LPR-based lower bounds. 9-17 - Subodh Gupta, Farid N. Najm:
Power modeling for high-level power estimation. 18-29 - Mohammed A. S. Khalid, Jonathan Rose:
A novel and efficient routing architecture for multi-FPGA systems. 30-39 - Darko Kirovski, Miodrag Potkonjak, Lisa M. Guerra:
Cut-based functional debugging for programmable systems-on-chip. 40-51 - Jer-Min Jou, Pei-Yin Chen, Sheng-Fu Yang:
An adaptive fuzzy logic controller: its VLSI architecture and applications. 52-60 - Yi-Min Jiang, Angela Krstic, Kwang-Ting Cheng:
Estimation for maximum instantaneous current through supply lines for CMOS circuits. 61-73 - Song Chen, Adam Postula:
Synthesis of custom interleaved memory systems. 74-83 - Alexander Marquardt, Vaughn Betz, Jonathan Rose:
Speed and area tradeoffs in cluster-based FPGA architectures. 84-93 - Uming Ko, Poras T. Balsara:
High-performance energy-efficient D-flip-flop circuits. 94-98 - Cristiana Bolchini, R. Montandon, Fabio Salice, Donatella Sciuto:
Design of VHDL-based totally self-checking finite-state machine and data-path descriptions. 98-103 - Wei-Chang Tsai, C. Bernard Shung, Sheng-Jyh Wang:
Two systolic architectures for modular multiplication. 103-107
Volume 8, Number 2, April 2000
- Marcelo Lubaszewski, Salvador Mir, Vladimir Kolarik, C. Nielsen, Bernard Courtois:
Design of self-checking fully differential circuits and boards. 113-128 - Thomas M. Conte, Kishore N. Menezes, Sumedh W. Sathaye, Mark C. Toburen:
System-level power consumption modeling and tradeoff analysis techniques for superscalar processor design. 129-137 - Scott Hauck, Matthew M. Hosler, Thomas W. Fry:
High-performance carry chains for FPGA's. 138-147 - Janardhan H. Satyanarayana, Keshab K. Parhi:
Theoretical analysis of word-level switching activity in the presence of glitching and correlation. 148-159 - Leilei Song, Keshab K. Parhi, Ichiro Kuroda, Takao Nishitani:
Hardware/software codesign of finite field datapath for low-energy Reed-Solomon codecs. 160-172 - Jin-Hyuk Yang, Byoung-Woon Kim, Sang-Joon Nam, Young-Su Kwon, Dae-Hyun Lee, Jong-Yeol Lee, Chan-Soo Hwang, Yong Hoon Lee, Seung Ho Hwang, In-Cheol Park, Chong-Min Kyung:
MetaCore: an application-specific programmable DSP development system. 173-183 - Johnny Öberg, Anshul Kumar, Ahmed Hemani:
Grammar-based hardware synthesis from port-size independent specifications. 184-194 - Yehea I. Ismail, Eby G. Friedman:
Effects of inductance on the propagation delay and repeater insertion in VLSI circuits. 195-206 - Frederik Vermeulen, Francky Catthoor, Diederik Verkest, Hugo De Man:
Formalized three-layer system-level model and reuse methodology for embedded data-dominated applications. 207-216 - David Kinniment, Alexandre Yakovlev, B. Gao:
Synchronous and asynchronous A-D conversion. 217-220 - Ronald D. Blanton, John P. Hayes:
On the design of fast, easily testable ALU's. 220-223 - Tapan J. Chakraborty, Vishwani D. Agrawal, Michael L. Bushnell:
Path delay fault simulation of sequential circuits. 223-228
Volume 8, Number 3, June 2000
- Kaushik Roy, D. T. Lee:
Guest editorial: low-power electronics and design. 233-234 - Azeez J. Bhavnagarwala, Blanca Austin, Keith A. Bowman, James D. Meindl:
A minimum total power methodology for projecting limits on CMOS GSI. 235-251 - Abram P. Dancy, Rajeevan Amirtharajah, Anantha P. Chandrakasan:
High-efficiency multiple-output DC-DC conversion for low-voltage systems. 252-263 - Hui Zhang, George Varghese, Jan M. Rabaey:
Low-swing on-chip signaling techniques: effectiveness and robustness. 264-272 - J. Y. F. Tong, David Nagle, Rob A. Rutenbar:
Reducing power by optimizing the necessary precision/range of floating-point arithmetic. 273-286 - Luca Benini, Giovanni De Micheli, Alberto Macii, Enrico Macii, Massimo Poncino, Riccardo Scarsi:
Glitch power minimization by selective gate freezing. 287-298 - Luca Benini, Alessandro Bogliolo, Giovanni De Micheli:
A survey of design techniques for system-level dynamic power management. 299-316 - Nikolaos Bellas, Ibrahim N. Hajj, Constantine D. Polychronopoulos, George I. Stamoulis:
Architectural and compiler techniques for energy reduction in high-performance microprocessors. 317-326 - Sari L. Coumeri, Donald E. Thomas:
Memory modeling for system synthesis. 327-334 - Diana Marculescu, Radu Marculescu, Massoud Pedram:
Theoretical bounds for switching activity analysis in finite-state machines. 335-339 - Brian A. White, Mohamed I. Elmasry:
Low-power design of decimation filters for a digital IF receiver. 339-345 - Dinesh Bhatia, James Haralambides:
Resource requirements and layouts for field programmable interconnection chips. 346-355 - Kenneth Y. Yun, Kevin W. James, Robert H. Fairlie-Cuninghame, Supratik Chakraborty, Rene L. Cruz:
A self-timed real-time sorting network. 356-363
Volume 8, Number 4, August 2000
- Jian Li, Rajesh K. Gupta:
HDL presynthesis optimizations using a tabular model. 369-378 - Rajamohana Hegde, Naresh R. Shanbhag:
Toward achieving energy efficiency in presence of deep submicron noise. 379-391 - Juinn-Dar Huang, Jing-Yang Jou, Wen-Zen Shen:
ALTO: an iterative area/performance tradeoff algorithm for LUT-based FPGA technology mapping. 392-400 - Toshiaki Miyazaki, Atsushi Takahara, Takahiro Murooka, Masaru Katayama, Takaki Ichimori, Kazuhiro Shirakawa, Akihiro Tsutsui, Ken-nosuke Fukami:
PROTEUS-Lite project: dedicated to developing a telecommunication-oriented FPGA and its applications. 401-414 - Alessandro Bogliolo, Michele Favalli, Maurizio Damiani:
Enabling testability of fault-tolerant circuits by means of IDDQ-checkable voters. 415-419 - H. T. Nguyen, A. Chattejee:
Number-splitting with shift-and-add decomposition for power and hardware optimization in linear DSP synthesis. 419-424 - Gin Yee, Carl Sechen:
Clock-delayed domino for dynamic circuit design. 425-430 - Mehrdad Nourani, Christos A. Papachristou:
Stability-based algorithms for high-level synthesis of digital ASICs. 431-435 - Michael S. Hsiao, Elizabeth M. Rudnick, Janak H. Patel:
Peak power estimation of VLSI circuits: new peak power measures. 435-439 - Oscal T.-C. Chen, Wei-Lung Liu:
An FIR processor with programmable dynamic data ranges. 440-446 - Samuel Norman Hamilton, Alex Orailoglu:
On-line test for fault-secure fault identification. 446-452 - Eckart Zitzler, Jürgen Teich, Shuvra S. Bhattacharyya:
Evolutionary algorithms for the synthesis of embedded software. 452-455 - Johnny Pihl:
Design automation with the TSPC circuit technique: a high-performance wave digital filter. 456-460 - Dragan Maksimovic, Vojin G. Oklobdzija, Borivoje Nikolic, K. Wayne Current:
Clocked CMOS adiabatic logic with integrated single-phase power-clock supply. 460-463
Volume 8, Number 5, October 2000
- Allen C.-H. Wu, Nikil D. Dutt:
Guest editorial 11th international symposium on system-level synthesis and design (ISSS'98). 469-471 - Petru Eles, Alex Doboli, Paul Pop, Zebo Peng:
Scheduling with bus access optimization for distributed embedded systems. 472-491 - Sungjoo Yoo, Kiyoung Choi, Dong Sam Ha:
Performance improvement of geographically distributed cosimulation by hierarchically grouped messages. 492-502 - Jin-Hua Hong, Chung-Hung Tsai, Cheng-Wen Wu:
Hierarchical system test by an IEEE 1149.5 MTM-bus slave-module interface core. 503-516 - Ying Zhao, Sharad Malik:
Exact memory size estimation for array computations. 517-521 - Wonyong Sung, Soonhoi Ha:
Memory efficient software synthesis with mixed coding style from dataflow graphs. 522-526 - Dominique Borrione, Julia Dushina, Laurence V. Pierre:
A compositional model for the functional verification of high-level synthesis results. 526-530 - Guido Araujo, Paulo Centoducatte, Rodolfo Azevedo, Ricardo Pannain:
Expression-tree-based algorithms for code compression on embedded RISC architectures. 530-533 - Bassam Shaer, Sami A. Al-Arian, David L. Landis:
Partitioning sequential circuits for pseudoexhaustive testing. 534-541 - Montek Singh, Steven M. Nowick:
Synthesis for logical initializability of synchronous finite-state machines. 542-557 - Christian Pacha, Uwe Auer, Christian Burwick, Peter Glösekötter, Andreas Brennemann, Werner Prost, Franz-Josef Tegude, Karl F. Goser:
Threshold logic circuit design of parallel adders using resonant tunneling devices. 558-572 - Allen E. Sjogren, Chris J. Myers:
Interfacing synchronous and asynchronous modules within a high-speed pipeline. 573-583 - Chih-Shun Ding, Cheng-Ta Hsieh, Massoud Pedram:
Improving the efficiency of Monte Carlo power estimation [VLSI]. 584-593 - Han Bin Kim, Dong Sam Ha, Takeshi Takahashi, Takahiro J. Yamaguchi:
A new approach to built-in self-testable datapath synthesis based on integer linear programming. 594-605 - Fabrice Caignet, S. D.-B. Dhia, Etienne Sicard:
On the measurement of crosstalk in integrated circuits. 606-609 - Ananta K. Majhi, V. D. Agrawak, James Jacob, Lalit M. Patnaik:
Line coverage of path delay faults. 610-614 - Pasquale Corsonello, Stefania Perri, G. Cororullo:
Area-time-power tradeoff in cellular arrays VLSI implementations. 614-624 - Antonio G. M. Strollo, Ettore Napoli, Carlo Cimino:
Analysis of power dissipation in double edge-triggered flip-flops. 624-629 - Chingwei Yeh, Yin-Shuin Kang:
Cell-based layout techniques supporting gate-level voltage scaling for low power. 629-633 - Krishnendu Chakrabarty, Brian T. Murray, Vikram Iyengar:
Deterministic built-in test pattern generation for high-performance circuits using twisted-ring counters. 633-636
Volume 8, Number 6, December 2000
- Phillip Christie, Dirk Stroobandt:
The interpretation and application of Rent's rule. 639-648 - Payman Zarkesh-Ha, Jeffrey A. Davis, James D. Meindl:
Prediction of net-length distribution for global interconnects in a heterogeneous system-on-a-chip. 649-659 - Sek M. Chai, Tarek M. Taha, D. Scott Wills, James D. Meindl:
Heterogeneous architecture models for interconnect-motivated system design. 660-670 - Arifur Rahman, Rafael Reif:
System-level performance evaluation of three-dimensional integrated circuits. 671-678 - Phillip Christie:
Rent exponent prediction methods. 679-688 - Qiang Chen, Jeffrey A. Davis, Payman Zarkesh-Ha, James D. Meindl:
A compact physical via blockage model. 689-692 - Nikolaos Bellas, Ibrahim N. Hajj, Constantine D. Polychronopoulos:
Using dynamic cache management techniques to reduce energy in general purpose processors. 693-708 - Eric Gayles, Thomas P. Kelliher, Robert Michael Owens, Mary Jane Irwin:
The design of the MGAP-2: a micro-grained massively parallel array. 709-716 - Ali Keshavarzi, Kaushik Roy, Charles F. Hawkins:
Intrinsic leakage in deep submicron CMOS ICs-measurement-based test solutions. 717-723 - Santanu Chattopadhyay, Shelly Adhikari, Sabyasachi Sengupta, Mahua Pal:
Highly regular, modular, and cascadable design of cellular automata-based pattern classifier. 724-735 - Tapan J. Chakraborty, Vishwani D. Agrawal, Michael L. Bushnell:
Improving path delay testability of sequential circuits. 736-741 - Donald L. Hung, Heng-Da Cheng, Savang Sengkhamyong:
Design of a configurable accelerator for moment computation. 741-746 - Chittaranjan A. Mandal, P. P. Chakrabarti, Sujoy Ghose:
GABIND: a GA approach to allocation and binding for the high-level synthesis of data paths. 747-750 - Bassam Shaer, David L. Landis, Sami A. Al-Arian:
Partitioning algorithm to enhance pseudoexhaustive testing of digital VLSI circuits. 750-754
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