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ORCIDShunli Ma
This is just a disambiguation page, and is not intended to be the bibliography of an actual person. Any publication listed on this page has not been assigned to an actual author yet. If you know the true author of one of the publications listed below, you are welcome to contact us.
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Journal Articles
- 2023
[j15]Xi Wang, Dong Wei, Zhiyang Zhang, Tianxiang Wu, Xu Chen, Yong Chen
, Junyan Ren, Shunli Ma:
A 90- to 115-GHz superheterodyne receiver front-end for W-band imaging system in 28-nm complementary metal-oxide-semiconductor. Int. J. Circuit Theory Appl. 51(4): 1530-1547 (2023)- [j14]Miao Sun, Yingjie Cao, Jian Qian, Jie Li, Sifan Zhou, Ziyu Zhao, Yifan Wu, Tao Xia, Yajie Qin, Lei Qiu, Shunli Ma, Patrick Yin Chiang, Shenglong Zhuo:
A 40nm 2TOPS/W Depth-Completion Neural Network Accelerator SoC With Efficient Depth Engine for Realtime LiDAR Systems. IEEE Trans. Circuits Syst. II Express Briefs 70(5): 1704-1708 (2023) - [j13]Yujia Wang, Jincheng Zhang, Yong Chen, Junyan Ren, Shunli Ma:
A 4.5-W, 18.5-24.5-GHz GaN Power Amplifier Employing Chebyshev Matching Technique. IEEE Trans. Very Large Scale Integr. Syst. 31(2): 233-242 (2023) - 2022
- [j12]Tianxiang Wu, Xi Wang, Yong Chen, Junyan Ren, Shunli Ma:
A 10-MHz to 50-GHz low-jitter multiphase clock generator for high-speed oscilloscope in 0.15-μm GaAs technology. Int. J. Circuit Theory Appl. 50(2): 367-381 (2022) - [j11]Zhiyang Zhang, Lihe Nie, Jincheng Zhang, Tianxiang Wu, Yong Chen, Junyan Ren, Shunli Ma:
A 23- to 28-GHz 5-bit switch-type phase shifter with 1-bit calibration based on optimized ABCD matrix design methods for 5G MIMO system in 0.15-μm GaAs. Int. J. Circuit Theory Appl. 50(6): 1834-1854 (2022) - [j10]Jincheng Zhang, Lihe Nie, Yong Chen, Junyan Ren, Shunli Ma:
A 6.5-mm2 10.5-to-15.5-GHz Differential GaN PA With Coupled-Line-Based Matching Networks Achieving 10-W Peak Psat and 42% PAE. IEEE Trans. Circuits Syst. II Express Briefs 69(11): 4268-4272 (2022) - 2021
- [j9]Dong Wei, Xuan Ding, Hai Yu, Yen-Cheng Kuan, Qun Jane Gu, Zhiwei Xu, Shunli Ma, Junyan Ren:
Analysis and Design of a 35-GHz Hybrid π-Network High-Gain Phase Shifter With 360° Continuous Phase Shifting. IEEE Access 9: 11943-11953 (2021) - [j8]Jincheng Zhang, Tianxiang Wu, Lihe Nie, Shunli Ma, Yong Chen, Junyan Ren:
A 120-150 GHz Power Amplifier in 28-nm CMOS Achieving 21.9-dB Gain and 11.8-dBm Psat for Sub-THz Imaging System. IEEE Access 9: 74752-74762 (2021) - [j7]Manxin Li, Yuting Yao, Biao Hu, Jipeng Wei, Yong Chen, Shunli Ma, Fan Ye, Junyan Ren:
A 6.94-fJ/Conversion-Step 12-bit 100-MS/s Asynchronous SAR ADC Exploiting Split-CDAC in 65-nm CMOS. IEEE Access 9: 77545-77554 (2021) - [j6]Shunli Ma, Yi Deng, Debiao He, Jiang Zhang, Xiang Xie:
An Efficient NIZK Scheme for Privacy-Preserving Transactions Over Account-Model Blockchain. IEEE Trans. Dependable Secur. Comput. 18(2): 641-651 (2021) - [j5]Shunli Ma, Tianxiang Wu, Jincheng Zhang, Junyan Ren:
A 5G Wireless Event-Driven Sensor Chip for Online Power-Line Disturbances Detecting Network in 0.25 μm GaAs Process. IEEE Trans. Ind. Electron. 68(6): 5271-5280 (2021) - 2020
- [j4]Shunli Ma, Yan Wang, Xinyu Chen, Tianxiang Wu, Xi Wang, Hongwei Tang, Yuting Yao, Hao Yu, Yaochen Sheng, Jingyi Ma, Junyan Ren, Wenzhong Bao:
Analog Integrated Circuits Based on Wafer-Level Two-Dimensional MoS2 Materials With Physical and SPICE Model. IEEE Access 8: 197287-197299 (2020) - [j3]Shunli Ma, Tianxiang Wu, Junyan Ren:
A Quadrature PLL With Phase Mismatch Calibration for 32GS/s Time-Interleaved ADC. IEEE Access 8: 219695-219708 (2020) - 2019
- [j2]Shunli Ma, Hao Yu, Qun Jane Gu, Junyan Ren:
A 5-10-Gb/s 12.5-mW Source Synchronous I/O Interface With 3-D Flip Chip Package. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(2): 555-568 (2019) - 2018
- [j1]Shunli Ma, Ning Li, Junyan Ren:
A 5-to-8-GHz Wideband Miniaturized Dielectric Spectroscopy Chip With $I/Q$ Mismatch Calibration in 65-nm CMOS. IEEE Trans. Very Large Scale Integr. Syst. 26(8): 1554-1564 (2018)
Conference and Workshop Papers
- 2024
- [c37]Ziyang Shen, Xiaoxu Xie, Chaoming Fang, Fengshi Tian, Shunli Ma, Jie Yang, Mohamad Sawan:
NeuroSORT: A Neuromorphic Accelerator for Spike-based Online and Real-time Tracking. AICAS 2024: 312-316 - 2023
- [c36]Xiaodi Feng, Shunli Ma, Muxi Zou, Tianxiang Wu:
A High Gain and Wide Bandwidth Dual-Power CMOS Op-amp for High-Speed ADCs Application. ASICON 2023: 1-4 - [c35]Cai Tian, Tianxiang Wu, Shunli Ma, Wenzhong Bao:
An Improved Delay Cell with Low Power Consumption and Strong Driving Capability. ASICON 2023: 1-4 - [c34]Yigang Wei, Tianxiang Wu, Shunli Ma, Junyan Ren:
A Multi-channel 12-bits 100MS/s SAR ADC in 65nm CMOS. ASICON 2023: 1-4 - [c33]Lei Wu, Junyan Ren, Tianxiang Wu, Shunli Ma:
A 15GHz Class-C VCO with Two-stage Buffer in 0.15-μm GaAs. ASICON 2023: 1-4 - [c32]Jing Yuan, Wenzhong Bao, Tianxiang Wu, Shunli Ma:
High Performance Bootstrap Switch for 14 bit SAR ADC with Redundancy in SMIC 180nm. ASICON 2023: 1-4 - [c31]Muxi Zou, Shunli Ma, Xiaodi Feng, Junyan Ren, Tianxiang Wu:
A 300MS/s 57.6dB SNDR Single-Channel SAR ADC with Accelerated SAR Logic. ASICON 2023: 1-4 - 2022
- [c30]Wenyang Liu, Tianxiang Wu, Tianyang Yan, Fan Yang, Yong Chen, Shunli Ma:
A 26-38GHz Ultra-Wideband Balanced Frequency Doubler in 0.15µ m GaAs pHEMT Process. APCCAS 2022: 337-340 - [c29]Zhiyang Zhang, Xi Wang, Yong Chen, Junyan Ren, Shunli Ma:
A 60-GHz CMOS Balanced Power Amplifier with Miniaturized Quadrature Hybrids Achieving 19.0-dBm Output Power and 24.4% Peak PAE. APCCAS 2022: 560-564 - [c28]Zhiyang Zhang, Xi Wang, Junyan Ren, Shunli Ma:
A Two-Way Current-Combining W-band Power Amplifier Achieving 17.4-dBm Output Power with 19.4% PAE in 65-nm Bulk CMOS. ISCAS 2022: 2215-2219 - [c27]Xi Wang, Zhiyang Zhang, Junyan Ren, Shunli Ma:
A 134-154 GHz Low-Noise Amplifier Achieving 36.3-dB Maximum Gain with 3.8-dB Minimum Noise Figure for D-Band Imaging System. MWSCAS 2022: 1-5 - 2021
- [c26]Yi Deng, Shunli Ma, Xinxuan Zhang, Hailong Wang, Xuyang Song, Xiang Xie:
Promise $\varSigma $-Protocol: How to Construct Efficient Threshold ECDSA from Encryptions Based on Class Groups. ASIACRYPT (4) 2021: 557-586 - [c25]Xu Chen, Junyan Ren, Shunli Ma:
A 79GHz 5-bit Phase Shifter With π-Network in 28-nm CMOS. ASICON 2021: 1-4 - [c24]Xi Wang, Junyan Ren, Shunli Ma:
An 4th-order N-path Bandpass Filter with a Tuning Range of 1-30 GHz and OOB Rejection > 30 dB in 28 nm CMOS. ASICON 2021: 1-4 - [c23]Zhiyang Zhang, Junyan Ren, Shunli Ma:
A C-Band Power Amplifier with Over-Neutralization Technique and Coupled-Line MCR Matching Methods for 5G Communication in 0.25-μm GaAs. ASICON 2021: 1-4 - [c22]Jincheng Zhang, Tianxiang Wu, Yong Chen, Junyan Ren, Shunli Ma:
A 3-to-78GHz Differential Distributed Amplifier with Ultra- Balanced Active Balun and Gain Boosting Techniques in 65-nm CMOS Process. A-SSCC 2021: 1-3 - [c21]Dong Wei, Tianxiang Wu, Shunli Ma, Yong Chen, Junyan Ren:
A 35-to-50 GHz CMOS Low-Noise Amplifier with 22.2% -1-dB Fractional Bandwidth and 30.5-dB Maximum Gain for 5G New Radio. ESSCIRC 2021: 195-198 - 2020
- [c20]Jincheng Zhang, Lihe Nie, Shunli Ma, Junyan Ren:
A 10-18 GHz GaN Power Amplifier Based on Asymmetric Magnetically Coupled Resonator. MWSCAS 2020: 802-805 - [c19]Shunli Ma, Yi Deng, Mengqiu Bai, Debiao He, Jiang Zhang, Xiang Xie:
A Practical NIZK Argument for Confidential Transactions over Account-Model Blockchain. ProvSec 2020: 234-253 - 2019
- [c18]Dong Wei, Jincheng Zhang, Tianxiang Wu, Shunli Ma, Junyan Ren:
A 22-40.5 GHz UWB LNA Design in 0.15um GaAs. ASICON 2019: 1-4 - [c17]Tianxiang Wu, Jincheng Zhang, Dong Wei, Lihe Nie, Yuting Yao, Shunli Ma, Junyan Ren:
A 36-40 GHz VCO with bonding inductors for millimeter wave 5G Communication. ASICON 2019: 1-4 - [c16]Yuting Yao, Manxin Li, Tianxiang Wu, Hu Xu, Shunli Ma, Wenzhong Bao, Junyan Ren:
SPICE Modeling and Simulation of High-Performance Wafer-Scale MoS2 Transistors. ASICON 2019: 1-4 - [c15]Yuting Yao, Jipeng Wei, Manxin Li, Shunli Ma, Fan Ye, Junyan Ren:
A 256MHz Analog Baseband Chain with tunable Bandwidth and Gain for UWB Receivers. ASICON 2019: 1-4 - [c14]Jincheng Zhang, Lihe Nie, Dong Wei, Tianxiang Wu, Shunli Ma, Junyan Ren:
A 130-150 GHz Power Amplifier for Millimeter Wave Imaging in 65-nm CMOS. ASICON 2019: 1-4 - [c13]Jipeng Wei, Yuting Yao, Longheng Luo, Shunli Ma, Fan Ye, Junyan Ren:
A Novel Nauta Transconductor for Ultra-Wideband gm-C Filter with Temperature Calibration. ISCAS 2019: 1-4 - [c12]Dong Wei, Xuan Ding, Hai Yu, Bo Yu, Shunli Ma, Qun Jane Gu, Junyan Ren:
A 140 GHz, 4 dB Noise-Figure Low-Noise Amplifier Design with the Compensation of Parasitic Capacitance CGS. MWSCAS 2019: 299-302 - 2017
- [c11]Shunli Ma, Jili Sheng, Ning Li, Junyan Ren:
A 7GHz-bandwidth 31.5 GHz FMCW-PLL with novel twin-VCOs structure in 65nm CMOS. A-SSCC 2017: 321-324 - 2015
- [c10]Fazhi An, Shunli Ma, Qian Chen, Guangyao Zhou, Fan Ye, Junyan Ren:
A wide-division-ratio 100MHz-to-5GHz multi-modulus divider chain for wide-band PLL. ASICON 2015: 1-4 - [c9]Qian Chen, Fazhi An, Guangyao Zhou, Shunli Ma, Fan Ye, Junyan Ren:
A 39 GHz-80 GHz millimeter-wave frequency doubler with low power consumption in 65nm CMOS tehnology. ASICON 2015: 1-4 - [c8]Guangyao Zhou, Shunli Ma, Fazhi An, Ning Li, Fan Ye, Junyan Ren:
A 30-GHz to 39-GHz mm-Wave low-power injection-locked frequency divider in 65nm CMOS. ASICON 2015: 1-4 - [c7]Shunli Ma, Guangyao Zhou, Jianbing Jiang, Chixiao Chen, Yongzhen Chen, Fan Ye, Junyan Ren:
A quadrature clock generator with calibration for 22∼31.4 GS/s real-time sampling system. ESSCIRC 2015: 136-139 - 2014
- [c6]Shunli Ma, Hao Yu, Yang Shang, Wei Meng Lim, Junyan Ren:
A 131.5GHz, -84dBm sensitivity super-regenerative receiver by zero-phase-shifter coupled oscillator network in 65nm CMOS. ESSCIRC 2014: 187-190 - [c5]Guoxian Dai, Chixiao Chen, Shunli Ma, Fan Ye, Junyan Ren:
A 400-MS/s 8-b 2-b/cycle SAR ADC with shared interpolator and alternative comparators. ISCAS 2014: 2365-2368 - [c4]Shunli Ma, Junyan Ren, Hao Yu:
An overview of new design techniques for high performance CMOS millimeter-wave circuits. ISIC 2014: 292-295 - 2013
- [c3]Jiacheng Wang, Shunli Ma, Sai Manoj Pudukotai Dinakarrao, Mingbin Yu, Roshan Weerasekera, Hao Yu:
High-speed and low-power 2.5D I/O circuits for memory-logic-integration by through-silicon interposer. 3DIC 2013: 1-4 - [c2]Shunli Ma, Wei Fei, Hao Yu, Junyan Ren:
A 75.7GHz to 102GHz rotary-traveling-wave VCO by tunable composite right /left hand T-line. CICC 2013: 1-4 - 2012
- [c1]Shunli Ma, Changming Chen, Yiwen Zhang, Junyan Ren:
A low power programmable band-pass filter with novel pseudo-resistor for portable biopotential acquisition system. APCCAS 2012: 232-235
Informal and Other Publications
- 2022
- [i2]Yi Deng, Shunli Ma, Xinxuan Zhang, Hailong Wang, Xuyang Song, Xiang Xie:
Promise Σ-protocol: How to Construct Efficient Threshold ECDSA from Encryptions Based on Class Groups. IACR Cryptol. ePrint Arch. 2022: 297 (2022) - 2017
- [i1]Shunli Ma, Yi Deng, Debiao He, Jiang Zhang, Xiang Xie:
An Efficient NIZK Scheme for Privacy-Preserving Transactions over Account-Model Blockchain. IACR Cryptol. ePrint Arch. 2017: 1239 (2017)
Coauthor Index
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