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ORCIDWalid M. Hafez
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2020 – today
- 2024
[c6]Walid M. Hafez, D. Abanulo, M. Abdelkader, S. An, C. Auth, D. Bahr, V. Balakrishnan, R. Bambery, M. Beck, M. Bhargava, S. Bhowmick, J. Biggs-houck, J. Birdsall, D. Caselli, H.-Y. Chang, Y. Chang, R. Chaudhuri, S. Chauhan, C. Chen, V. Chikarmane, K. Chikkadi, T. Chu, C. Connor, R. De Alba, Y. Deng, C. Destefano, D. Diana, Y. Dong, P. Elfick, Tyler Elko-Hansen, B. Fallahazad, Y. Fang, D. Gala, D. Garg, C. Geppert, S. Govindaraju, W. Grimm, H. Grunes, L. Guler, Z. Guo, A. Gupta, M. Hattendorf, S. Havelia, J. Hazra, A. Islam, A. Jain, S. Jaloviar, M. Jamil, M. Jang, M. Kabir, J. Kameswaran, Eric Karl, S. Kelgeri, A. Kennedy, C. Kilroy, J. Kim, Y. Kim, D. Krishnan, G. Lee, H.-P. Lee, Q. Li, H. Lin, A. Luk, Y. Luo, P. Macfarlane, A. Mamun, K. Marla, D. Mayeri, E. Mckenna, A. Miah, K. Mistry, M. Mleczko, S. Moon, D. Nardi, S. Natarajan, J. Nathawat, C. Nolph, C. Nugroho, P. Nyhus, A. Oni, P. Packan, D. Pak, A. Paliwal, R. Pandey, I. Paredes, K. Park, L. Paulson, A. Pierre, P. Plekhanov, C. Prasad, R. Ramaswamy, J. Riley, Johann Rode, R. Russell, S. Ryu, H. Saavedra, T. Salisbury, Justin Sandford, F. Shah, K. Shang, P. Shekhar, A. Shu, E. Skoug, J. Sohn, J. Song, M. Sprinkle, J. Su, A. Tan, T. Troeger, R. Tsao, A. Vaidya, C. Wallace, X. Wang, H. Wang, C. Ward, S. Wickramaratne, M. Wills, T. Wu, Z. Xia-hua, S. Xu, P. Yashar, J. Yaung, Y. Yu, M. Zilm, Bernhard Sell:
An Intel 3 Advanced FinFET Platform Technology for High Performance Computing and SOC Product Applications. VLSI Technology and Circuits 2024: 1-2- 2023
- [c5]Walid M. Hafez, P. Agnihotri, M. Asoro, M. Aykol, B. Bains, R. Bambery, M. Bapna, A. Barik, A. Chatterjee, P. C. Chiu, T. Chu, C. Firby
, K. Fischer, M. Fradkin, Hannes Greve, A. Gupta, E. Haralson, M. Haran, Jeffery Hicks, A. Illa, M. Jang, S. Klopcic, M. Kobrinsky, B. Kuns, H.-h. Lai, G. Lanni, S.-H. Lee, N. Lindert, C.-l. Lo, Y. Luo, G. Malyavanatham, B. Marinkovic, Y. Maymon, M. Nabors, J. Neirynck, P. Packan, A. Paliwal, L. Pantisano, Leif Paulson, Padma Penmatsa, Chetan Prasad, Conor Puls, T. Rahman, R. Ramaswamy, S. Samant, Bernhard Sell, K. Sethi, F. Shah, M. Shamanna, K. Shang, Q. Li, M. Sibakoti, J. Stoeger, Nathan Strutt, R. Thirugnanasambandam, C. Tsai, X. Wang, A. Wang, S.-j. Wu, Q. Xu, X.-h. Zhong, S. Natarajan:
Intel PowerVia Technology: Backside Power Delivery for High Density and High-Performance Computing. VLSI Technology and Circuits 2023: 1-2 - [c4]M. Shamanna, E. Abuayob, G. Aenuganti, C. Alvares, J. Antony, A. Bahudhanam, A. Chandran, P. Chew, A. Chatterjee, B. Chauhan, N. Dandeti, J. Desai, M. Doyle, T. Dmukauskas, P. Farache, E. Fetzer, K. Fischer, P. Hack, Y. Greenzweig, John Giacobbe, Walid M. Hafez, E. Haralson, A. Hegde, A. Illa, M. Islam, S. Jain, M. Jang, J. Nguyen, T. Tong, L. Jiang, Eric Karl, P. Kalangi, G. Khoo, A. Krishnamoorthy, B. Kuns, W. Li, R. Livengood, T. Malik, R. Priyanka, H. Faraby, Y. Maymon, K. Mistry, K. Morgan, S. Natarajan, O. Nevo, M. Oh, P. Pardy, J. Park, P. Penmatsa, Boyd Phelps, C. Peterson, S. Rajappa, A. Raveh, A Rezaie, T. Ravishankar, R. Ramaswamy, S. Reddy, R. Saha, S. Sen, R. Sanchez, R. Sanaga, B. Simkhovich, Bernhard Sell, M. Senger, B. Schnarch, M. Seshadri, O. Sidorov, S. Subramanian, K. Subramanian, B. Truong, S. Bangalore, Jeffery Hicks, S. Venkatesh, D. Christensen, K. Bhargav, M. Von Haartman, P. Joshi, S. Zickel, C.-H. Lin, J. Huening, T.-H. Wu, N. Bakken, A. Afzal, A. Raman, Sj. Rao, V. Kawar, J. Neirynck, D. Bradley, M. Duwe, S. Wu, V. Patil, M. Bayoumy:
E-Core Implementation in Intel 4 with PowerVia (Backside Power) Technology. VLSI Technology and Circuits 2023: 1-2 - 2022
- [c3]Bernhard Sell, S. An, J. Armstrong, D. Bahr, B. Bains, R. Bambery, K. Bang, D. Basu, S. Bendapudi, D. Bergstrom, R. Bhandavat, S. Bhowmick, M. Buehler, D. Caselli, S. Cekli, Vrsk. Chaganti, Y. J. Chang, K. Chikkadi, T. Chu, T. Crimmins, G. Darby, C. Ege, P. Elfick, Tyler Elko-Hansen, S. Fang, C. Gaddam, M. Ghoneim, H. Gomez, S. Govindaraju, Z. Guo, Walid M. Hafez, M. Haran, M. Hattendorf, S. Hu, A. Jain, S. Jaloviar, M. Jang, J. Kameswaran, V. Kapinus, A. Kennedy, S. Klopcic, D. Krishnan, J. Leib, Y.-T. Lin, N. Lindert, G. Liu, O. Loh, Y. Luo, S. Mani, M. Mleczko, S. Mocherla, P. Packan, M. Paik, A. Paliwal, R. Pandey, K. Patankar, L. Pipes, P. Plekhanov, Chetan Prasad, M. Prince, G. Ramalingam, R. Ramaswamy, J. Riley, J. R. Sanchez Perez, Justin Sandford, A. Sathe, F. Shah, H. Shim, S. Subramanian, S. Tandon, M. Tanniru, D. Thakurta, T. Troeger, X. Wang, C. Ward, A. Welsh, S. Wickramaratne, J. Wnuk, S. Q. Xu, P. Yashar, J. Yaung, K. Yoon, N. Young:
Intel 4 CMOS Technology Featuring Advanced FinFET Transistors optimized for High Density and High-Performance Computing. VLSI Technology and Circuits 2022: 282-283
2010 – 2019
- 2015
- [c2]Chia-Hong Jan, F. Al-amoody, H.-Y. Chang, T. Chang, Y.-W. Chen, N. Dias, Walid M. Hafez, Doug B. Ingerly, M. Jang, Eric Karl, S. K.-Y. Shi, K. Komeyli, H. Kilambi, A. Kumar, K. Byon, C.-G. Lee, J. Lee, T. Leo, P.-C. Liu, N. Nidhi, R. Olac-vaw, C. Petersburg, K. Phoa, Chetan Prasad, C. Quincy, R. Ramaswamy, T. Rana, L. Rockford, Aravinth Subramaniam, C. Tsai, Peter Vandervoorn, L. Yang, A. Zainuddin, Peng Bai:
A 14 nm SoC platform technology featuring 2nd generation Tri-Gate transistors, 70 nm gate pitch, 52 nm metal pitch, and 0.0499 um2 SRAM cells, optimized for low power, high performance and high density SoC products. VLSIC 2015: 12-
2000 – 2009
- 2008
- [j1]Yih Wang, Hong Jo Ahn, Uddalak Bhattacharya, Zhanping Chen, Tom Coan, Fatih Hamzaoglu, Walid M. Hafez, Chia-Hong Jan, Pramod Kolar, Sarvesh H. Kulkarni, Jie-Feng Lin, Yong-Gee Ng, Ian Post, Liqiong Wei, Ying Zhang, Kevin Zhang, Mark Bohr:
A 1.1 GHz 12 µA/Mb-Leakage SRAM Design in 65 nm Ultra-Low-Power CMOS Technology With Integrated Leakage Reduction for Mobile Applications. IEEE J. Solid State Circuits 43(1): 172-179 (2008) - 2007
- [c1]Yih Wang, Hong Jo Ahn, Uddalak Bhattacharya, Tom Coan, Fatih Hamzaoglu, Walid M. Hafez, Chia-Hong Jan, Pramod Kolar, Sarvesh H. Kulkarni, Jie-Feng Lin, Yong-Gee Ng, Ian Post, Liqiong Wei, Yih Zhang, Kevin Zhang, Mark Bohr:
A 1.1GHz 12μA/Mb-Leakage SRAM Design in 65nm Ultra-Low-Power CMOS with Integrated Leakage Reduction for Mobile Applications. ISSCC 2007: 324-606 - 2005
- [b1]Walid M. Hafez:
Submicron Scaling of Indium Phosphide/indium Gallium Arsenide Heterojunction Bipolar Transistors Toward Terahertz Bandwidths. University of Illinois Urbana-Champaign, USA, 2005
Coauthor Index
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