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2020 – today
- 2023
[j3]Chenlei Fang
, Qicheng Huang, Zeye Liu, Ruizhou Ding, Ronald D. Blanton:
Efficient Test Chip Design via Smart Computation. ACM Trans. Design Autom. Electr. Syst. 28(2): 22:1-22:31 (2023)- 2021
- [c16]Chenlei Fang, Qicheng Huang, R. D. Shawn Blanton:
Memory-Efficient Adaptive Test Pattern Reordering for Accurate Diagnosis. VTS 2021: 1-7 - 2020
- [j2]Qicheng Huang, Chenlei Fang, Soumya Mittal, R. D. (Shawn) Blanton:
Towards Smarter Diagnosis: A Learning-based Diagnostic Outcome Previewer. ACM Trans. Design Autom. Electr. Syst. 25(5): 43:1-43:20 (2020) - [c15]Qicheng Huang, Chenlei Fang, R. D. Shawn Blanton:
LAIDAR: Learning for Accuracy and Ideal Diagnostic Resolution. ITC 2020: 1-10 - [c14]Qicheng Huang, Chenlei Fang, R. D. Shawn Blanton:
Knowledge Transfer for Diagnosis Outcome Preview with Limited Data. ITC 2020: 1-9 - [c13]Chenlei Fang, Qicheng Huang, R. D. Shawn Blanton:
Adaptive Test Pattern Reordering for Diagnosis using k-Nearest Neighbors. ITC-Asia 2020: 59-64 - [c12]Qicheng Huang, Chenlei Fang, R. D. Shawn Blanton:
Diagnosis Outcome Prediction on Limited Data via Transferred Random Forest. ITC-Asia 2020: 65-70
2010 – 2019
- 2019
- [c11]Qicheng Huang, Chenlei Fang, Zeye Liu, Ruizhou Ding, R. D. Shawn Blanton:
IPSA: Integer Programming via Sparse Approximation for Efficient Test-Chip Design. ICCD 2019: 11-19 - [c10]Zeye Liu, Qicheng Huang, Chenlei Fang, R. D. (Shawn) Blanton:
Improving Test Chip Design Efficiency via Machine Learning. ITC 2019: 1-10 - [c9]Chenlei Fang, Qicheng Huang, Soumya Mittal, R. D. Shawn Blanton:
Diagnosis Outcome Preview through Learning. VTS 2019: 1-6 - 2018
- [c8]Qicheng Huang, Chenlei Fang, Soumya Mittal, R. D. Shawn Blanton:
Improving Diagnosis Efficiency via Machine Learning. ITC 2018: 1-10 - 2016
- [j1]Qicheng Huang, Xiao Li, Chenlei Fang, Fan Yang, Yangfeng Su, Xuan Zeng:
An aggregating based model order reduction method for power grids. Integr. 55: 449-454 (2016) - [c7]Qicheng Huang, Chenlei Fang, Fan Yang, Xuan Zeng, Dian Zhou, Xin Li:
Efficient performance modeling via Dual-Prior Bayesian Model Fusion for analog and mixed-signal circuits. DAC 2016: 8:1-8:6 - [c6]Chenlei Fang, Qicheng Huang, Fan Yang, Xuan Zeng, Dian Zhou, Xin Li:
Efficient performance modeling of analog integrated circuits via kernel density based sparse regression. DAC 2016: 10:1-10:6 - [c5]Xuan Zeng, Chenlei Fang, Qicheng Huang, Fan Yang, Dian Zhou, Wei Cai, Weiping Shi:
High-speed link verification based on statistical inference. ISCAS 2016: 906-909 - 2015
- [c4]Qicheng Huang, Xiao Li, Chenlei Fang, Fan Yang, Yangfeng Su, Xuan Zeng:
PGMOR: An Efficient Model Order Reduction Method for Power Grids. CAD/Graphics 2015: 242-243 - [c3]Qicheng Huang, Chenlei Fang, Fan Yang, Xuan Zeng, Xin Li:
Efficient multivariate moment estimation via Bayesian model fusion for analog and mixed-signal circuits. DAC 2015: 169:1-169:6 - [c2]Chenlei Fang, Qicheng Huang, Fan Yang, Xuan Zeng, Xin Li, Chenjie Gu:
Efficient bit error rate estimation for high-speed link by Bayesian model fusion. DATE 2015: 1024-1029 - 2014
- [c1]Chenlei Fang, Fan Yang, Xuan Zeng, Xin Li:
BMF-BD: Bayesian Model Fusion on Bernoulli Distribution for Efficient Yield Estimation of Integrated Circuits. DAC 2014: 29:1-29:6
Coauthor Index
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