Integration, Volume 55

Volume 55, September 2016

Research Papers

• 
  T. Nandha Kumar, Haider A. F. Almurib, Fabrizio Lombardi:
  Design of a memristor-based look-up table (LUT) for low-energy operation of FPGAs. 1-11
• 
  Khawar Sarfraz, Mansun Chan:
  A compact low-power 4-port register file with grounded write bitlines and single-ended read operations. 12-21
• 
  Héctor Pettenghi, Ricardo Chaves, Roberto de Matos, Leonel Sousa:
  Method for designing two levels RNS reverse converters for large dynamic ranges. 22-29
• 
  Jingyang Zhu, Zhiliang Qian, Chi-Ying Tsui:
  BiLink: A high performance NoC router architecture using bi-directional link with double data rate. 30-42
• 
  M. Mohamed Asan Basiri, Sk. Noor Mahammad:
  Multi-mode parallel and folded VLSI architectures for 1D-fast Fourier transform. 43-56
• 
  Kourosh Hassanli, Sayed Masoud Sayedi, Rasoul Dehghani, Armin Jalili, J. Jacob Wikner:
  A low-power wide tuning-range CMOS current-controlled oscillator. 57-66
• 
  Yishai Statter, Tom Chen:
  Γ (Gamma): A SaaS-enabled fast and accurate analog design System. 67-84
• 
  Cinzia Bernardeschi, Luca Cassano, Andrea Domenici, Luca Sterpone:
  UA²TPG: An untestability analyzer and test pattern generator for SEUs in the configuration memory of SRAM-based FPGAs. 85-97
• 
  Mahdi Mosaffa, Siamak Mohammadi, Saeed Safari:
  Statistical analysis of asynchronous pipelines in presence of process variation using formal models. 98-117
• 
  Simone Orcioni, Marco Giammarini, Cristiano Scavongelli, Giovanni B. Vece, Massimo Conti:
  Energy estimation in SystemC with Powersim. 118-128
• 
  Wasim Hussain, Olivier Valorge, Yves Blaquière, Yvon Savaria:
  A novel spatially configurable differential interface for an electronic system prototyping platform. 129-137
• 
  Bahram Rashidi, Sayed Masoud Sayedi, Reza Rezaeian Farashahi:
  An efficient and high-speed VLSI implementation of optimal normal basis multiplication over GF(2^m). 138-154
• 
  Zeinab Torabi, Ghassem Jaberipur:
  Fast low energy RNS comparators for 4-moduli sets {2ⁿ±1, 2ⁿ, m} with m∈{2ⁿ⁺¹±1, 2^n-1-1}. 155-161
• 
  Hao Zhang, Dongyi Ye, Wenzhong Guo:
  A heuristic for constructing a rectilinear Steiner tree by reusing routing resources over obstacles. 162-175
• 
  Amir Albeck, Shmuel Wimer:
  Energy efficient computing by multi-mode addition. 176-182
• 
  Arezoo Kamran, Zainalabedin Navabi:
  Stochastic testing of processing cores in a many-core architecture. 183-193
• 
  Elahe Rastegar Pashaki, Majid Shalchian:
  Design and simulation of an ultra-low power high performance CMOS logic: DMTGDI. 194-201
• 
  Aysa Fakheri Tabrizi, Laleh Behjat, William Swartz, Logan M. Rakai:
  A fast force-directed simulated annealing for 3D IC partitioning. 202-211
• 
  Zeinab Hojati, Mohammad Yavari:
  An NTF-enhanced incremental ΣΔ modulator using a SAR quantizer. 212-219

Special section on The International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD 2015) for Integration, the VLSI Journal

• 
  O. Bellaaj Kchaou, Amel Garbaya, Mouna Kotti, Pedro Pereira, Mourad Fakhfakh, M. Helena Fino:
  Sensitivity aware NSGA-II based Pareto front generation for the optimal sizing of analog circuits. 220-226

Research Papers

• 
  H. C. Bandala-Hernandez, José Miguel Rocha-Pérez, Alejandro Díaz-Sánchez, Javier Lemus-López, Héctor Vázquez-Leal, Alejandra Díaz-Armendariz, Jaime Ramírez-Angulo:
  Weighted median filters: An analog implementation. 227-231
• 
  Jian Kuang, Evangeline F. Y. Young:
  Row-structure stencil planning approaches for E-beam lithography with overlapped characters. 232-245
• 
  Lior Moyal, Itamar Levi, Adam Teman, Alexander Fish:
  Synthesis of Dual Mode Logic. 246-253
• 
  Uros Nahtigal, Drago Strle:
  Design, simulation, and implementation of an integrated, hybrid photocurrent-to-digital converter in CMOS technology. 254-264
• 
  Filipe Guimarães Russo Ramos, Tales Cleber Pimenta, Luis Henrique de Carvalho Ferreira:
  A mixed-signal pulse width modulator for portable SMPS applications. 265-273
• 
  Victor R. Gonzalez-Diaz, Luis Abraham Sánchez-Gaspariano, Carlos Muñiz-Montero, Jose J. Alvarado-Pulido:
  Improving linearity in MOS varactor based VCOs by means of the output quiescent bias point. 274-280
• 
  Mohammad Shokouhifar, Ali Jalali:
  Two-stage fuzzy inference system for symbolic simplification of analog circuits. 281-292

Special section on The International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD 2015) for Integration, the VLSI Journal;

• 
  Günhan Dündar, Nuno Horta, Francisco V. Fernández:
  Introduction to the special issue on SMACD 2015. 293-294
• 
  Ricardo Martins, Ricardo Povoa, Nuno Lourenço, Nuno Horta:
  Current-flow and current-density-aware multi-objective optimization of analog IC placement. 295-306
• 
  Xin Huang, Valeriy Sukharev, Jun-Ho Choy, Marko Chew, Taeyoung Kim, Sheldon X.-D. Tan:
  Electromigration assessment for power grid networks considering temperature and thermal stress effects. 307-315
• 
  Nuno Lourenço, Ricardo Martins, António Canelas, Ricardo Povoa, Nuno Horta:
  AIDA: Layout-aware analog circuit-level sizing with in-loop layout generation. 316-329
• 
  Mrinalinee Pandey, António Canelas, Ricardo Póvoa, Jorge Alves Torres, João Costa Freire, Nuno Lourenço, Nuno Horta:
  Design and application of a CMOS active inductor at Ku band based on a multi-objective optimizer. 330-340
• 
  Antonio Toro-Frías, Pablo Martín-Lloret, Javier Martín-Martínez, Rafael Castro-López, Elisenda Roca, Rosana Rodríguez, Montserrat Nafría, Francisco V. Fernández:
  Reliability simulation for analog ICs: Goals, solutions, and challenges. 341-348
• 
  Engin Afacan, Gönenç Berkol, Günhan Dündar, Ali Emre Pusane, I. Faik Baskaya:
  A lifetime-aware analog circuit sizing tool. 349-356
• 
  Murat Pak, Francisco V. Fernández, Günhan Dündar:
  Comparison of QMC-based yield-aware pareto front techniques for multi-objective robust analog synthesis. 357-365
• 
  Muharrem Orkun Saglamdemir, Gönenç Berkol, Günhan Dündar, Alper Sen:
  An analog behavioral equivalence boundary search methodology for simulink models and circuit level designs utilizing evolutionary computation. 366-375
• 
  Fanshu Jiao, Alex Doboli:
  Causal reasoning mining approach to analog circuit verification. 376-383
• 
  Giulia Di Capua, Nicola Femia, Gianpaolo Lisi:
  Impact of losses and mismatches on power and efficiency of Wireless Power Transfer Systems with controlled secondary-side rectifier. 384-392
• 
  Anthony Coyette, Baris Esen, Wim Dobbelaere, Ronny Vanhooren, Georges G. E. Gielen:
  Automatic generation of test infrastructures for analog integrated circuits by controllability and observability co-optimization. 393-400
• 
  Gildas Léger, Manuel J. Barragán:
  Brownian distance correlation-directed search: A fast feature selection technique for alternate test. 401-414
• 
  Álvaro Gómez-Pau, Luz Balado, Joan Figueras:
  Indirect test of M-S circuits using multiple specification band guarding. 415-424

Special section on The 14th International Conference on Computer-Aided Design and Computer Graphics (CAD/Graphics 2015)

• 
  Xin Li, Sheldon X.-D. Tan, Yu Wang:
  Editorial: Special Issue on The 14th International Conference on Computer-Aided Design and Computer Graphics (CAD/Graphics 2015). 425
• 
  He Li, Qiang Liu, Jiliang Zhang:
  A survey of hardware Trojan threat and defense. 426-437
• 
  Bao Liu, Gang Qu:
  VLSI supply chain security risks and mitigation techniques: A survey. 438-448
• 
  Qicheng Huang, Xiao Li, Chenlei Fang, Fan Yang, Yangfeng Su, Xuan Zeng:
  An aggregating based model order reduction method for power grids. 449-454
• 
  Lidong Xing, Tao Li, Hucai Huang, Qingsheng Zhang, Jungang Han:
  Efficient modeling and analysis of energy consumption for 3D graphics rendering. 455-464
• 
  Hui Geng, Jianming Liu, Jinglan Liu, Pei-Wen Luo, Liang-Chia Cheng, Steven L. Grant, Yiyu Shi:
  Selective body biasing for post-silicon tuning of sub-threshold designs: A semi-infinite programming approach with Incremental Hypercubic Sampling. 465-473