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ORCIDShao-Chun Hung
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2020 – today
- 2024
[j4]Shao-Chun Hung
, Arjun Chaudhuri, Sanmitra Banerjee, Krishnendu Chakrabarty:
Fault Diagnosis for Resistive Random Access Memory and Monolithic Inter-Tier Vias in Monolithic 3-D Integration. IEEE Trans. Very Large Scale Integr. Syst. 32(7): 1336-1349 (2024)- [c13]Shao-Chun Hung, Partho Bhoumik, Krishnendu Chakrabarty:
Testing and Fault Diagnosis for Multi-level Resistive Random-Access Memory in Monolithic 3D Integration. VTS 2024: 1-7 - 2023
- [j3]Shao-Chun Hung, Sanmitra Banerjee, Arjun Chaudhuri, Jinwoo Kim, Sung Kyu Lim, Krishnendu Chakrabarty:
Transferable Graph Neural Network-Based Delay-Fault Localization for Monolithic 3-D ICs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(11): 4296-4309 (2023) - [c12]Shao-Chun Hung, Arjun Chaudhuri, Krishnendu Chakrabarty:
Test-Point Insertion for Power-Safe Testing of Monolithic 3D ICs using Reinforcement Learning*. ETS 2023: 1-6 - [c11]Shao-Chun Hung, Arjun Chaudhuri, Sanmitra Banerjee, Krishnendu Chakrabarty:
Scan Cell Segmentation Based on Reinforcement Learning for Power-Safe Testing of Monolithic 3D ICs. ITC 2023: 216-225 - [c10]Shao-Chun Hung, Arjun Chaudhuri, Sanmitra Banerjee, Krishnendu Chakrabarty:
Special Session: Using Graph Neural Networks for Tier-Level Fault Localization in Monolithic 3D ICs *. VTS 2023: 1-4 - 2022
- [c9]Shao-Chun Hung, Sanmitra Banerjee, Arjun Chaudhuri, Krishnendu Chakrabarty:
Graph Neural Network-based Delay-Fault Localization for Monolithic 3D ICs. DATE 2022: 448-453 - [c8]Shao-Chun Hung, Sanmitra Banerjee, Arjun Chaudhuri, Krishnendu Chakrabarty:
Graph Neural Network-based Delay-Fault Localization for Monolithic 3D ICs. DATE 2022: 1311-1316 - [c7]Bonita Bhaskaran, Sanmitra Banerjee, Kaushik Narayanun, Shao-Chun Hung, Seyed Nima Mozaffari Mojaveri, Mengyun Liu, Gang Chen, Tung-Che Liang:
Observation Point Insertion Using Deep Learning. ICCAD 2022: 161:1-161:8 - [c6]Shao-Chun Hung, Arjun Chaudhuri, Sanmitra Banerjee, Krishnendu Chakrabarty:
Fault Diagnosis for Resistive Random-Access Memory and Monolithic Inter-tier Vias in Monolithic 3D Integration. ITC 2022: 118-127 - 2021
- [j2]Chen-Hao Hsu, Shao-Chun Hung, Hao Chen, Fan-Keng Sun, Yao-Wen Chang:
A DAG-Based Algorithm for Obstacle-Aware Topology-Matching On-Track Bus Routing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(3): 533-546 (2021) - [j1]Shao-Chun Hung, Yi-Chen Lu, Sung Kyu Lim, Krishnendu Chakrabarty:
Power Supply Noise-Aware At-Speed Delay Fault Testing of Monolithic 3-D ICs. IEEE Trans. Very Large Scale Integr. Syst. 29(11): 1875-1888 (2021) - [c5]Sanmitra Banerjee, Arjun Chaudhuri, Shao-Chun Hung, Krishnendu Chakrabarty:
Advances in Testing and Design-for-Test Solutions for M3D Integrated Circuits. DATE 2021: 152-157 - 2020
- [c4]Shao-Chun Hung, Yi-Chen Lu, Sung Kyu Lim, Krishnendu Chakrabarty:
Power Supply Noise-Aware Scan Test Pattern Reshaping for At-Speed Delay Fault Testing of Monolithic 3D ICs *. ATS 2020: 1-6 - [c3]Shao-Chun Hung, Krishnendu Chakrabarty:
Design of a Reliable Power Delivery Network for Monolithic 3D ICs*. DATE 2020: 1746-1751
2010 – 2019
- 2019
- [c2]Hao Chen, Shao-Chun Hung, Jie-Hong R. Jiang:
Disjoint-Support Decomposition and Extraction for Interconnect-Driven Threshold Logic Synthesis. DAC 2019: 73 - [c1]Chen-Hao Hsu, Shao-Chun Hung, Hao Chen, Fan-Keng Sun, Yao-Wen Chang:
A DAG-Based Algorithm for Obstacle-Aware Topology-Matching On-Track Bus Routing. DAC 2019: 217
Coauthor Index
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