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2020 – today
- 2021
[j13]José L. Núñez-Yáñez, Mohammad Hosseinabady:
Sparse and dense matrix multiplication hardware for heterogeneous multi-precision neural networks. Array 12: 100101 (2021)- 2020
- [j12]Mohammad Hosseinabady
, José Luis Núñez-Yáñez:
A Streaming Dataflow Engine for Sparse Matrix-Vector Multiplication Using High-Level Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(6): 1272-1285 (2020) - [c33]Mohammad Hosseinabady, José L. Núñez-Yáñez:
Sparse Matrix-Dense Matrix Multiplication on Heterogeneous CPU+FPGA Embedded System. PARMA-DITAM@HiPEAC 2020: 1:1-1:6 - [c32]José L. Núñez-Yáñez, Kris Nikov, Kerstin Eder, Mohammad Hosseinabady:
Run-Time Power Modelling in Embedded GPUs with Dynamic Voltage and Frequency Scaling. PARMA-DITAM@HiPEAC 2020: 2:1-2:6 - [i5]José L. Núñez-Yáñez, Kris Nikov, Kerstin Eder, Mohammad Hosseinabady:
Run-Time Power Modelling in Embedded GPUs with Dynamic Voltage and Frequency Scaling. CoRR abs/2006.12176 (2020) - [i4]Kris Nikov, Mohammad Hosseinabady, Rafael Asenjo, Andrés Rodríguez, Angeles G. Navarro, José L. Núñez-Yáñez:
High-Performance Simultaneous Multiprocessing for Heterogeneous System-on-Chip. CoRR abs/2008.08883 (2020)
2010 – 2019
- 2019
- [j11]José L. Núñez-Yáñez, Sam Amiri, Mohammad Hosseinabady, Andrés Rodríguez, Rafael Asenjo, Angeles G. Navarro, Darío Suárez Gracia, Ruben Gran:
Simultaneous multiprocessing in a software-defined heterogeneous FPGA. J. Supercomput. 75(8): 4078-4095 (2019) - [j10]José L. Núñez-Yáñez, Sam Amiri, Mohammad Hosseinabady, Andrés Rodríguez, Rafael Asenjo, Angeles G. Navarro, Darío Suárez Gracia, Ruben Gran:
Correction to: Simultaneous multiprocessing in a software-defined heterogeneous FPGA. J. Supercomput. 75(8): 4096-4097 (2019) - [i3]Mohammad Hosseinabady, Mohd Amiruddin Bin Zainol, José L. Núñez-Yáñez:
Heterogeneous FPGA+GPU Embedded Systems: Challenges and Opportunities. CoRR abs/1901.06331 (2019) - 2018
- [j9]Mohammad Hosseinabady, José Luis Núñez-Yáñez:
Dynamic Energy Management of FPGA Accelerators in Embedded Systems. ACM Trans. Embed. Comput. Syst. 17(3): 63:1-63:26 (2018) - [c31]Sam Amiri, Mohammad Hosseinabady, Simon McIntosh-Smith, José L. Núñez-Yáñez:
Multi-precision convolutional neural networks on heterogeneous hardware. DATE 2018: 419-424 - [c30]Sam Amiri, Mohammad Hosseinabady, Andrés Rodríguez, Rafael Asenjo, Angeles G. Navarro, José L. Núñez-Yáñez:
Workload Partitioning Strategy for Improved Parallelism on FPGA-CPU Heterogeneous Chips. FPL 2018: 376-380 - [i2]José L. Núñez-Yáñez, Mohammad Hosseinabady, Moslem Amiri, Andrés Rodríguez, Rafael Asenjo, Angeles G. Navarro, Ruben Gran Tejero, Darío Suárez Gracia:
Parallelizing Workload Execution in Embedded and High-Performance Heterogeneous Systems. CoRR abs/1802.03316 (2018) - 2017
- [c29]Mohammad Hosseinabady, José Luis Núñez-Yáñez:
A systematic approach to design and optimise streaming applications on FPGA using high-level synthesis. FPL 2017: 1-4 - [c28]Mohammad Hosseinabady, José Luis Núñez-Yáñez:
Pipelined Streaming Computation of Histogram in FPGA OpenCL. PARCO 2017: 632-641 - [c27]José L. Núñez-Yáñez, Mohammad Hosseinabady, Andrés Rodríguez, Rafael Asenjo, Angeles G. Navarro, Ruben Gran Tejero, Darío Suárez Gracia:
Simultaneous Multiprocessing on a FPGA+CPU Heterogeneous System-On-Chip. PARCO 2017: 677-686 - 2016
- [j8]José Luis Núñez-Yáñez, Mohammad Hosseinabady, Arash Beldachi:
Energy Optimization in Commercial FPGAs with Voltage, Frequency and Logic Scaling. IEEE Trans. Computers 65(5): 1484-1493 (2016) - 2015
- [c26]Mohammad Hosseinabady, José Luis Núñez-Yáñez:
Energy optimization of FPGA-based stream-oriented computing with power gating. FPL 2015: 1-6 - [c25]Mohammad Hosseinabady, José Luis Núñez-Yáñez:
Optimised OpenCL workgroup synthesis for hybrid ARM-FPGA devices. FPL 2015: 1-6 - 2014
- [c24]Mohammad Hosseinabady, José Luis Núñez-Yáñez:
Run-time power gating in hybrid ARM-FPGA devices. FPL 2014: 1-6 - 2012
- [j7]Mohammad Hosseinabady, José Luis Núñez-Yáñez:
Run-time stochastic task mapping on a large scale network-on-chip with dynamically reconfigurable tiles. IET Comput. Digit. Tech. 6(1): 1-11 (2012) - [j6]Mohammad Hosseinabady, José Luis Núñez-Yáñez:
Fast and low overhead architectural transaction level modelling for large-scale network-on-chip simulation. IET Comput. Digit. Tech. 6(6): 384-395 (2012) - [c23]José L. Núñez-Yáñez, Arash Beldachi, Atukem Nabina, Mohammad Hosseinabady:
Exploring dynamically reconfigurable multicore designs with NoRC designer. HPCS 2012: 254-260 - 2011
- [j5]Mohammad Hosseinabady, Mohammad Reza Kakoee, Jimson Mathew, Dhiraj K. Pradhan:
Low Latency and Energy Efficient Scalable Architecture for Massive NoCs Using Generalized de Bruijn Graph. IEEE Trans. Very Large Scale Integr. Syst. 19(8): 1469-1480 (2011) - [c22]Mohammad Hosseinabady, Pejman Lotfi-Kamran, Jimson Mathew, Saraju P. Mohanty, Dhiraj K. Pradhan:
Single-Event Transient Analysis in High Speed Circuits. ISED 2011: 112-117 - 2010
- [c21]Mohammad Hosseinabady, José L. Núñez-Yáñez:
SystemC Architectural Transaction Level Modelling for Large NoCs. FDL 2010: 142-147 - [c20]Mohammad Hosseinabady, José L. Núñez-Yáñez:
Effective modelling of large NoCs using SystemC. ISCAS 2010: 161-164 - [c19]Mohammad Hosseinabady, José Luis Núñez-Yáñez, Antonio Marcello Coppola:
Task Dispersal Measurement in Dynamic Reconfigurable NoCs. ISVLSI 2010: 167-172
2000 – 2009
- 2009
- [c18]José L. Núñez-Yáñez, Mohammad Hosseinabady, Atukem Nabina, Izhar Zaidi:
Energy optimization in a Network-on-Chip with dynamically reconfigurable processing nodes. CCA/ISIC 2009: 308-313 - [c17]Mohammad Hosseinabady, José L. Núñez-Yáñez:
Run-time resource management in fault-tolerant network on reconfigurable chips. FPL 2009: 574-577 - 2008
- [j4]Mohammad Hosseinabady, Shervin Sharifi, Fabrizio Lombardi, Zainalabedin Navabi:
A Selective Trigger Scan Architecture for VLSI Testing. IEEE Trans. Computers 57(3): 316-328 (2008) - [c16]Mohammad Hosseinabady, José L. Núñez-Yáñez:
Fault-tolerant dynamically reconfigurable NoC-based SoC. ASAP 2008: 31-36 - [c15]Mohammad Hosseinabady, Mohammad Reza Kakoee, Jimson Mathew, Dhiraj K. Pradhan:
De Bruijn Graph as a Low Latency Scalable Architecture for Energy Efficient Massive NoCs. DATE 2008: 1370-1373 - [c14]Jimson Mathew, Jawar Singh, Abusaleh M. Jabir, Mohammad Hosseinabady, Dhiraj K. Pradhan:
Fault tolerant bit parallel finite field multipliers using LDPC codes. ISCAS 2008: 1684-1687 - 2007
- [j3]Mohammad Hosseinabady, Pejman Lotfi-Kamran, Fabrizio Lombardi, Zainalabedin Navabi:
Low overhead DFT using CDFG by modifying controller. IET Comput. Digit. Tech. 1(4): 322-333 (2007) - [j2]Mohammad Hosseinabady, Pejman Lotfi-Kamran, Zainalabedin Navabi:
Low test application time resource binding for behavioral synthesis. ACM Trans. Design Autom. Electr. Syst. 12(2): 16 (2007) - [c13]Jawar Singh, Jimson Mathew, Mohammad Hosseinabady, Dhiraj K. Pradhan:
Single Event Upset Detection and Correction. ICIT 2007: 13-18 - [c12]Mohammad Hosseinabady, Atefe Dalirsani, Zainalabedin Navabi:
Using the inter- and intra-switch regularity in NoC switch testing. DATE 2007: 361-366 - [c11]Mohammad Hosseinabady, Mohammad Reza Kakoee, Jimson Mathew, Dhiraj K. Pradhan:
Reliable network-on-chip based on generalized de Bruijn graph. HLDVT 2007: 3-10 - [c10]Atefe Dalirsani, Mohammad Hosseinabady, Zainalabedin Navabi:
An Analytical Model for Reliability Evaluation of NoC Architectures. IOLTS 2007: 49-56 - [c9]Mohammad Hosseinabady, Mohammad Hossein Neishaburi, Zainalabedin Navabi, Alfredo Benso, Stefano Di Carlo, Paolo Prinetto, Giorgio Di Natale:
Analysis of System-Failure Rate Caused by Soft-Errors using a UML-Based Systematic Methodology in an SoC. IOLTS 2007: 205-206 - [c8]Mohammad Hosseinabady, Mohammad Hossein Neishaburi, Pejman Lotfi-Kamran, Zainalabedin Navabi:
A UML Based System Level Failure Rate Assessment Technique for SoC Designs. VTS 2007: 243-248 - [i1]Shervin Sharifi, Javid Jaffari, Mohammad Hosseinabady, Ali Afzali-Kusha, Zainalabedin Navabi:
Simultaneous Reduction of Dynamic and Static Power in Scan Structures. CoRR abs/0710.4653 (2007) - 2006
- [j1]Shervin Sharifi, Javid Jaffari, Mohammad Hosseinabady, Ali Afzali-Kusha, Zainalabedin Navabi:
Scan-Based Structure with Reduced Static and Dynamic Power Consumption. J. Low Power Electron. 2(3): 477-487 (2006) - [c7]Mohammad Hosseinabady, Abbas Banaiyan, Mahdi Nazm Bojnordi, Zainalabedin Navabi:
A concurrent testing method for NoC switches. DATE 2006: 1171-1176 - [c6]Mohammad Hosseinabady, Pejman Lotfi-Kamran, Giorgio Di Natale, Stefano Di Carlo, Alfredo Benso, Paolo Prinetto:
Single-Event Upset Analysis and Protection in High Speed Circuits. ETS 2006: 29-34 - 2005
- [c5]Pejman Lotfi-Kamran, Mohammad Hosseinabady, Hamid Shojaei, Mehran Massoumi, Zainalabedin Navabi:
TED+: a data structure for microprocessor verification. ASP-DAC 2005: 567-572 - [c4]Shervin Sharifi, Javid Jaffari, Mohammad Hosseinabady, Ali Afzali-Kusha, Zainalabedin Navabi:
Simultaneous Reduction of Dynamic and Static Power in Scan Structures. DATE 2005: 846-851 - [c3]Mohammad Hosseinabady, Pejman Lotfi-Kamran, Pedram A. Riahi, Fabrizio Lombardi, Zainalabedin Navabi:
A Flow Graph Technique for DFT Controller Modification. SoCC 2005: 55-60 - 2003
- [c2]Shervin Sharifi, Mohammad Hosseinabady, Pedram A. Riahi, Zainalabedin Navabi:
Reducing Test Power, Time and Data Volume in SoC Testing Using Selective Trigger Scan Architecture. DFT 2003: 352-360 - [c1]Shervin Sharifi, Mohammad Hosseinabady, Zainalabedin Navabi:
Selective Trigger Scan Architecture for Reducing Power, Time and Data Volume in SoC Testing. VLSI-SOC 2003: 215-220
Coauthor Index
aka: José Luis Núñez-Yáñez
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