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ORCIDArkadiy Morgenshtein
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2010 – 2019
- 2017
[j7]Wisam Kadry, Dmitry Krestyashyn, Arkadiy Morgenshtein
, Amir Nahir, Vitali Sokhin, Jin Sung Park, Sung-Boem Park, Wookyeong Jeong, Jae-Cheol Son:
Test Generation Methods for Utilization Improvement of Hardware-Accelerated Simulation Platforms. IEEE Des. Test 34(1): 65-76 (2017)- 2016
- [c14]Doowon Lee, Tom Kolan, Arkadiy Morgenshtein, Vitali Sokhin, Ronny Morad, Avi Ziv, Valeria Bertacco:
Probabilistic bug-masking analysis for post-silicon tests in microprocessor verification. DAC 2016: 24:1-24:6 - 2015
- [c13]Wisam Kadry, Dmitry Krestyashyn, Arkadiy Morgenshtein, Amir Nahir, Vitali Sokhin, Jin Sung Park, Sung-Boem Park, Wookyeong Jeong, Jae-Cheol Son:
Comparative study of test generation methods for simulation accelerators. DATE 2015: 321-324 - 2014
- [j6]Arkadiy Morgenshtein, Viacheslav Yuzhaninov, Alexey Kovshilovsky, Alexander Fish:
Full-Swing Gate Diffusion Input logic - Case-study of low-power CLA adder design. Integr. 47(1): 62-70 (2014) - [c12]Ophir Friedler, Wisam Kadry, Arkadiy Morgenshtein, Amir Nahir, Vitali Sokhin:
Effective post-silicon failure localization using dynamic program slicing. DATE 2014: 1-6 - 2010
- [j5]Arkadiy Morgenshtein, Eby G. Friedman, Ran Ginosar, Avinoam Kolodny:
Unified Logical Effort - A Method for Delay Evaluation and Minimization in Logic Paths With RC Interconnect. IEEE Trans. Very Large Scale Integr. Syst. 18(5): 689-696 (2010) - [j4]Arkadiy Morgenshtein, Eby G. Friedman, Ran Ginosar, Avinoam Kolodny:
Corrections to "Unified Logical Effort - A Method for Delay Evaluation and Minimization in Logic Paths With RC Interconnect" [May 10 689-696]. IEEE Trans. Very Large Scale Integr. Syst. 18(8): 1262 (2010)
2000 – 2009
- 2008
- [c11]Arkadiy Morgenshtein, Eby G. Friedman, Ran Ginosar, Avinoam Kolodny:
Timing optimization in logic with interconnect. SLIP 2008: 19-26 - [c10]Rostislav (Reuven) Dobkin, Arkadiy Morgenshtein, Avinoam Kolodny, Ran Ginosar:
Parallel vs. serial on-chip communication. SLIP 2008: 43-50 - 2006
- [j3]Michael Moreinis, Arkadiy Morgenshtein, Israel A. Wagner, Avinoam Kolodny:
Logic Gates as Repeaters (LGR) for Area-Efficient Timing Optimization. IEEE Trans. Very Large Scale Integr. Syst. 14(11): 1276-1281 (2006) - 2005
- [c9]Arkadiy Morgenshtein, Israel Cidon, Ran Ginosar, Avinoam Kolodny:
Low-leakage repeaters for NoC interconnects. ISCAS (1) 2005: 600-603 - 2004
- [j2]Arkadiy Morgenshtein, Michael Moreinis, Ran Ginosar:
Asynchronous gate-diffusion-input (GDI) circuits. IEEE Trans. Very Large Scale Integr. Syst. 12(8): 847-856 (2004) - [c8]Michael Moreinis, Arkadiy Morgenshtein, Israel A. Wagner, Avinoam Kolodny:
Repeater insertion combined with LGR methodology for on-chip interconnect timing optimization. ICECS 2004: 125-128 - [c7]Evgeny Bolotin, Arkadiy Morgenshtein, Israel Cidon, Ran Ginosar, Avinoam Kolodny:
Automatic hardware-efficient SoC integration by QoS network on chip. ICECS 2004: 479-482 - [c6]Arkadiy Morgenshtein, Evgeny Bolotin, Israel Cidon, Avinoam Kolodny, Ran Ginosar:
Micro-modem - reliability solution for NoC communications. ICECS 2004: 483-486 - [c5]Liby Sudakov-Boreysha, Arkadiy Morgenshtein, Uri Dinnar, Yael Nemirovsky:
ISFET CMOS compatible design and encapsulation challenges. ICECS 2004: 535-538 - [c4]Arkadiy Morgenshtein, Alexander Fish, Israel A. Wagner:
An efficient implementation of D-Flip-Flop using the GDI technique. ISCAS (2) 2004: 673-676 - [c3]Arkadiy Morgenshtein, Israel Cidon, Avinoam Kolodny, Ran Ginosar:
Comparative analysis of serial vs parallel links in NoC. SoC 2004: 185-188 - 2003
- [c2]Arkadiy Morgenshtein, Michael Moreinis, Israel A. Wagner, Avinoam Kolodny:
Logic Gates as Repeaters (LGR) for Timing Optimization of SoC Interconnects. VLSI-SOC 2003: 99-104 - 2002
- [j1]Arkadiy Morgenshtein, Alexander Fish, Israel A. Wagner:
Gate-diffusion input (GDI): a power-efficient method for digital combinatorial circuits. IEEE Trans. Very Large Scale Integr. Syst. 10(5): 566-581 (2002) - [c1]Arkadiy Morgenshtein, Alexander Fish, Israel A. Wagner:
Gate-diffusion input (GDI) - a technique for low power design of digital circuits: analysis and characterization. ISCAS (1) 2002: 477-480
Coauthor Index
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