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2010 – 2019
- 2017
[j24]Hwang-Cherng Chow, Prasenjit Chatterjee, Wu-Shiung Feng:
A Simple Drain Current Model for MOS Transistors with the Lorentz Force Effect. Sensors 17(6): 1199 (2017)- 2016
- [j23]Prasenjit Chatterjee, Hwang-Cherng Chow, Wu-Shiung Feng:
Drain Current Modulation of a Single Drain MOSFET by Lorentz Force for Magnetic Sensing Application. Sensors 16(9): 1389 (2016)
2000 – 2009
- 2008
- [j22]Chia-Chi Chu
, Ming-Hong Lai, Wu-Shiung Feng:
Model-order reductions for MIMO systems using global Krylov subspace methods. Math. Comput. Simul. 79(4): 1153-1164 (2008) - [c30]Chen-Yuan Chu, Chien-Cheng Wei, Hui-Chen Hsu, Shu-Hau Feng, Wu-Shiung Feng:
A 24GHz low-power CMOS receiver design. ISCAS 2008: 980-983 - 2007
- [j21]Ming-Hong Lai, Chia-Chi Chu, Wu-Shiung Feng:
On the Equivalent of Structure Preserving Reductions Approach and Adjoint Networks Approach for VLSI Interconnect Reductions. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 90-A(2): 411-414 (2007) - [j20]Chia-Chi Chu, Ming-Hong Lai, Wu-Shiung Feng:
Lyapunov-Based Error Estimations of MIMO Interconnect Reductions by Using the Global Arnoldi Algorithm. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 90-A(2): 415-418 (2007) - [c29]Ming-Hong Lai, Chia-Chi Chu, Wu-Shiung Feng:
Applications of AOGL Model-Order Reduction Techniques in Interconnect Analysis. ISCAS 2007: 1133-1136 - 2006
- [j19]Chia-Chi Chu, Herng-Jer Lee, Ming-Hong Lai, Wu-Shiung Feng:
An Adjoint Network Approach for RLCG Interconnect Model Order Reductions. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 89-A(2): 439-447 (2006) - [j18]Chia-Chi Chu, Ming-Hong Lai, Wu-Shiung Feng:
MIMO Interconnects Order Reductions by Using the Multiple Point Adaptive-Order Rational Global Arnoldi Algorithm. IEICE Trans. Electron. 89-C(6): 792-802 (2006) - [j17]Chia-Chi Chu, Ming-Hong Lai, Wu-Shiung Feng:
The Multiple Point Global Lanczos Method for Multiple-Inputs Multiple-Outputs Interconnect Order Reductions. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 89-A(10): 2706-2716 (2006) - [j16]Ying-Haw Shu, Shing Tenqchen, Ming-Chang Sun, Wu-Shiung Feng:
A Brief Comparison of Two-phase and NOR-based Four-phase Pipelined Asynchronous Systems. J. Inf. Sci. Eng. 22(4): 941-952 (2006) - [j15]Ying-Haw Shu, Shing Tenqchen, Ming-Chang Sun, Wu-Shiung Feng:
XNOR-based double-edge-triggered flip-flop for two-phase pipelines. IEEE Trans. Circuits Syst. II Express Briefs 53-II(2): 138-142 (2006) - [c28]Ming-Hong Lai, Chia-Chi Chu, Wu-Shiung Feng:
The Multiple Point Global Lanczos Method for MIMO Interconnect Model-Order Reductions. APCCAS 2006: 1268-1271 - [c27]Ming-Hong Lai, Chia-Chi Chu, Wu-Shiung Feng:
Model-Order Reduction Algorithm with Structure Preserving Techniques. APCCAS 2006: 1607-1610 - [c26]Chia-Chi Chu, Ming-Hong Lai, Wu-Shiung Feng:
The global Lanczos method for MIMO interconnect order reductions. ISCAS 2006 - [c25]Ming-Hong Lai, Chia-Chi Chu, Wu-Shiung Feng:
MIMO interconnects order reductions by using the global Arnoldi algorithm. ISCAS 2006 - 2005
- [j14]Chia-Chi Chu, Herng-Jer Lee, Wu-Shiung Feng:
Error Estimations of Arnoldi-Based Interconnect Model-Order Reductions. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 88-A(2): 533-537 (2005) - [j13]Ming-Chang Sun, Ying-Haw Shu, Shing Tenqchen, Wu-Shiung Feng:
A One-Step Input Matching Method for Cascode CMOS Low-Noise Amplifiers. IEICE Trans. Electron. 88-C(3): 420-428 (2005) - [j12]Herng-Jer Lee, Chia-Chi Chu, Ming-Hong Lai, Wu-Shiung Feng:
Moment Computations of Distributed Coupled RLC Interconnects with Applications to Estimating Crosstalk Noise. IEICE Trans. Electron. 88-C(6): 1186-1195 (2005) - [j11]Chia-Chi Chu, Ming-Hong Lai, Wu-Shiung Feng:
Perturbation Approach for Order Selections of Two-Sided Oblique Projection-Based Interconnect Reductions. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 88-A(12): 3573-3576 (2005) - [c24]Hwang-Cherng Chow, Bo-Wei Chen, Hsiao-Chen Chen, Wu-Shiung Feng:
A 1.8 V, 0.3 mW, 10-bit SA-ADC with new self-timed timing control for biomedical applications. ISCAS (1) 2005: 736-739 - [c23]Chia-Chi Chu, Herng-Jer Lee, Wu-Shiung Feng, Ming-Hong Lai:
Interconnect model reductions by using the AORA algorithm with considering the adjoint network. ISCAS (2) 2005: 1278-1281 - 2004
- [c22]Ying-Haw Shu, Shing Tenqchen, Ming-Chang Sun, Wu-Shiung Feng:
An XNOR-based Double-edge-triggered Flip-Flop for Two-phase Pipelines. CCCT (1) 2004: 79-84 - [c21]Shing Tenqchen, Ying-Haw Shu, Ming-Chang Sun, Wu-Shiung Feng:
Blind Signal Extraction Algorithm for the License Plate Matching of Vehicle Positioning System. DELTA 2004: 440-442 - [c20]Herng-Jer Lee, Chia-Chi Chu, Wu-Shiung Feng:
Generalizations of adjoint networks technique for RLC interconnects model-order reductions. ISCAS (1) 2004: 185-188 - [c19]Herng-Jer Lee, Ming-Hong Lai, Chia-Chi Chu, Wu-Shiung Feng:
Applications of tree/link partitioning for moment computations of general lumped RLC networks with resistor loops. ISCAS (1) 2004: 713-716 - [c18]Herng-Jer Lee, Chia-Chi Chu, Wu-Shiung Feng:
Moment Computations of Nonuniform Distributed Coupled RLC Trees with Applications to Estimating Crosstalk Noise. ISQED 2004: 75-80 - 2003
- [j10]Herng-Jer Lee, Chia-Chi Chu, Wu-Shiung Feng:
Moment Computations of Lumped Coupled RLC Trees with Applications to Estimating Crosstalk Noise. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 86-A(12): 2952-2964 (2003) - [c17]Ming-Chang Sun, Shing Tenqchen, Ying-Haw Shu, Wu-Shiung Feng:
A 2.4 GHz CMOS image-reject low noise amplifier. ISCAS (1) 2003: 329-332 - [c16]Herng-Jer Lee, Chia-Chi Chu, Wu-Shiung Feng:
Interconnect modeling and sensitivity analysis using adjoint networks reduction technique. ISCAS (4) 2003: 648-651 - 2002
- [c15]Herng-Jer Lee, Chia-Chi Chu, Wu-Shiung Feng:
Crosstalk estimation in high-speed VLSI interconnect using coupled RLC-tree models. APCCAS (1) 2002: 257-262 - [c14]Chin Hsia, Ming-Hong Lai, Wu-Shiung Feng:
On-board effective inductance measurement. APCCAS (1) 2002: 443-446 - [c13]Shing Tenqchen, Ji-Horn Chang, Wu-Shiung Feng, Bor-Sheng Jeng:
Pipelining Extended Givens Rotation RLS Adaptive Filters. DELTA 2002: 466-473 - [c12]Herng-Jer Lee, Chia-Chi Chu, Wu-Shiung Feng:
Intelligent multipoint Arnoldi (IMA) approximations of FIR filters by low-order linear-phase IIR filters. ISCAS (1) 2002: 417-420 - 2001
- [c11]Chih-Chun Tang, Wen-Shih Lu, Lan-Da Van, Wu-Shiung Feng:
A 2.4-GHz CMOS down-conversion doubly balanced mixer with low supply voltage. ISCAS (4) 2001: 794-797 - 2000
- [j9]Cheng-Chung Hsu, Wu-Shiung Feng:
Testable design of multiple-stage OTA-C filters. IEEE Trans. Instrum. Meas. 49(5): 929-934 (2000) - [c10]Lan-Da Van, Chih-Chun Tang, Shing Tenqchen, Wu-Shiung Feng:
A new VLSI architecture without global broadcast for 2-D digital filters. ISCAS 2000: 547-550
1990 – 1999
- 1999
- [c9]Lan-Da Van, Shing Tenqchen, Chia-Hsun Chang, Wu-Shiung Feng:
A tree-systolic array of DLMS adaptive filter. ICASSP 1999: 1253-1256 - [c8]Lan-Da Van, Shuenn-Shyang Wang, Shing Tenqchen, Wu-Shiung Feng, Bor-Shenn Jeng:
Design of a lower-error fixed-width multiplier for speech processing application. ISCAS (3) 1999: 130-133 - 1995
- [j8]Chun-Jung Chen, Wu-Shiung Feng:
Relaxation-based transient sensitivity computations for MOSFET circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(2): 173-185 (1995) - 1994
- [j7]Jyh-Ming Wang, Sung-Chuan Fang, Wu-Shiung Feng:
New efficient designs for XOR and XNOR functions on the transistor level. IEEE J. Solid State Circuits 29(7): 780-786 (1994) - [c7]Chung-Jung Chen, Wu-Shiung Feng:
Transient Sensitivity Computation of MOSFET Circuits Using Iterated Timing Analysis and Selective-Tracing Waveform Eelaxation. DAC 1994: 581-585 - [c6]Jyh-Herng Wang, Jen-Teng Fan, Wu-Shiung Feng:
An Accurate Time-Domain Current Waveform Simulator for VLSI Circuits. EDAC-ETC-EUROASIC 1994: 562-566 - 1992
- [j6]Chia-Chun Tsai, Sao-Jie Chen, Wu-Shiung Feng:
An H-V alternating router. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11(8): 976-991 (1992) - [c5]Sung-Chuan Fang, Wu-Shiung Feng, Shian-Lang Lee:
A New Efficient Approach to Multilayer Channel Routing Problem. DAC 1992: 579-584 - 1991
- [j5]Pei-Yung Hsiao, S. F. Steven Chen, Chia-Chun Tsai, Wu-Shiung Feng:
A knowledge-based program for compacting mask layout of integrated circuits. Comput. Aided Des. 23(3): 223-231 (1991) - [c4]Sung-Chuan Fang, Kuo-En Chang, Wu-Shiung Feng, Sao-Jie Chen:
Constrained via Minimization with Practical Considerations for Multi-Layer VLSI/PCB Routing Problems. DAC 1991: 60-65 - [c3]Chun-Jung Chen, Jyuo-Min Shyu, Wu-Shiung Feng:
Transient Sensitivity Computation for Waveform Relaxation Based Timing Simulation. ICCAD 1991: 120-123 - 1990
- [j4]Chia-Chun Tsai, Sao-Jie Chen, Wu-Shiung Feng:
Generalized terminal connectivity problem for multilayer layout scheme. Comput. Aided Des. 22(7): 423-433 (1990) - [j3]Pei-Yung Hsiao, H. F. Steven Chen, Wu-Shiung Feng:
A new control strategy for an artificial intelligence approach to VLSI layout compaction. Integr. 10(1): 55-70 (1990) - [j2]Chia-Chun Tsai, Sao-Jie Chen, Wu-Shiung Feng:
An H-V Tile-Expansion Router. J. Inf. Sci. Eng. 6(3): 173-189 (1990) - [j1]Pei-Yung Hsiao, Wu-Shiung Feng:
Using a multiple storage quad tree on a hierarchical VLSI compaction scheme. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(5): 522-536 (1990)
1980 – 1989
- 1989
- [c2]S. F. Steven Chen, Pei-Yung Hsiao, Wu-Shiung Feng, Shun-Nan Dai, Wen-Zyh Wang:
The Control Model for a Knowledge-Based Approach to VLSI Compaction Design. IFIP Congress 1989: 241-246 - 1988
- [c1]Pei-Yung Hsiao, Chen Yung Syau, Wu-Shiung Feng, T. M. Parng, Cheng-Chung Hsu:
A rule-based compactor for VLSI/CAD mask layout. COMPSAC 1988: 35-42
Coauthor Index
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