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ORCIDMin Zhao 0001
Person information
- affiliation: Oracle America, Inc., Austin, TX, USA
- affiliation (2007 - 2010): Magma Design Automation, San Jose, CA, USA
- affiliation (1999 - 2007): Freescale Semiconductor, Inc., Austin, TX, USA
- affiliation (PhD 1999): University of Minnesota, Minneapolis, MN, USA
Other persons with the same name
- Min Zhao — disambiguation page
- Min Zhao 0002 — Beijing University of Posts and Telecommunications, Beijing Laboratory of Advanced Information Networks, China
- Min Zhao 0003
![[0000-0001-8208-118X]](https://dblp.dagstuhl.de/img/orcid-mark.12x12.png "0000-0001-8208-118X")
— Zhejiang Normal University, Department of Mathematics, Jinhua, China - Min Zhao 0004 — Nanjing University, School of Geographic and Oceanographic Sciences, China
- Min Zhao 0005 — Sichuan University, School of Electronics and Information Engineering, Chengdu, China
- Min Zhao 0006 — University of the Sunshine Coast, Sippy Downs, Australia (and 2 more)
- Min Zhao 0007 — Taiyuan University of Technology, College of Mathematics, China
- Min Zhao 0008 — Wenzhou University, College of Life and Environmental Science, Wenzhou, China
- Min Zhao 0009 — University of Pittsburgh, Department of Computer Science, Pittsburgh, PA, USA
- Min Zhao 0010 — Chongqing University, School of Automation, Chongqing, China
- Min Zhao 0011 — Nanjing University of Aeronautics and Astronautics, College of Automation Engineering, China
- Min Zhao 0012 — Taiyuan University of Technology, MoE Key Laboratory of Interface Science and Engineering in Advanced Materials, China (and 1 more)
- Min Zhao 0013 — Tsinghua University, Beijing, China (and 1 more)
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2010 – 2019
- 2010
[j7]Xiaoji Ye, Peng Li, Min Zhao, Rajendran Panda, Jiang Hu:
Scalable Analysis of Mesh-Based Clock Distribution Networks Using Application-Specific Reduced Order Modeling. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(9): 1342-1353 (2010)
2000 – 2009
- 2008
- [j6]Cheng Zhuo, Jiang Hu, Min Zhao, Kangsheng Chen:
Power Grid Analysis and Optimization Using Algebraic Multigrid. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(4): 738-751 (2008) - [c20]Xiaoji Ye, Min Zhao, Rajendran Panda, Peng Li, Jiang Hu:
Accelerating Clock Mesh Simulation Using Matrix-Level Macromodels and Dynamic Time Step Rounding. ISQED 2008: 627-632 - 2007
- [c19]Min Zhao, Rajendran Panda, Ben Reschke, Yuhong Fu, Trudi Mewett, Sri Chandrasekaran, Savithri Sundareswaran, Shu Yan:
On-Chip Decoupling Capacitance and P/G Wire Co-optimization for Dynamic Noise. DAC 2007: 162-167 - [c18]Xiaoji Ye, Peng Li, Min Zhao, Rajendran Panda, Jiang Hu:
Analysis of large clock meshes via harmonic-weighted model order reduction and port sliding. ICCAD 2007: 627-631 - [c17]Yuhong Fu, Rajendran Panda, Ben Reschke, Savithri Sundareswaran, Min Zhao:
A novel technique for incremental analysis of on-chip power distribution networks. ICCAD 2007: 817-823 - 2006
- [j5]Min Zhao, Yuhong Fu, Vladimir Zolotov, Savithri Sundareswaran, Rajendran Panda:
Optimal placement of power-supply pads and pins. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(1): 144-154 (2006) - [c16]Min Zhao, Rajendran Panda, Savithri Sundareswaran, Shu Yan, Yuhong Fu:
A fast on-chip decoupling capacitance budgeting algorithm using macromodeling and linear programming. DAC 2006: 217-222 - [c15]Cheng Zhuo, Jiang Hu, Min Zhao, Kangsheng Chen:
Fast decap allocation based on algebraic multigrid. ICCAD 2006: 107-111 - 2005
- [c14]Di Wu, Jiang Hu, Min Zhao, Rabi N. Mahapatra:
Timing driven track routing considering coupling capacitance. ASP-DAC 2005: 1156-1159 - 2004
- [c13]Di Wu, Jiang Hu, Rabi N. Mahapatra, Min Zhao:
Layer assignment for crosstalk risk minimization. ASP-DAC 2004: 159-162 - [c12]Min Zhao, Yuhong Fu, Vladimir Zolotov, Savithri Sundareswaran, Rajendran Panda:
Optimal placement of power supply pads and pins. DAC 2004: 165-170 - [c11]V. Seth, Min Zhao, Jiang Hu:
Exploiting level sensitive latches in wire pipelining. ICCAD 2004: 283-290 - 2003
- [j4]Haitian Hu, David T. Blaauw, Vladimir Zolotov, Kaushik Gala, Min Zhao, Rajendran Panda, Sachin S. Sapatnekar:
Fast on-chip inductance simulation using a precorrected-FFT method. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(1): 49-66 (2003) - [c10]Aseem Agarwal, David T. Blaauw, Vladimir Zolotov, Savithri Sundareswaran, Min Zhao, Kaushik Gala, Rajendran Panda:
Statistical delay computation considering spatial correlations. ASP-DAC 2003: 271-276 - [c9]Haitian Hu, David T. Blaauw, Vladimir Zolotov, Kaushik Gala, Min Zhao, Rajendran Panda, Sachin S. Sapatnekar:
Table look-up based compact modeling for on-chip interconnect timing and noise analysis. ISCAS (4) 2003: 668-671 - 2002
- [j3]Min Zhao, Rajendran Panda, Sachin S. Sapatnekar, David T. Blaauw:
Hierarchical analysis of power distribution networks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(2): 159-168 (2002) - [j2]Min Zhao, Sachin S. Sapatnekar:
Technology mapping algorithms for domino logic. ACM Trans. Design Autom. Electr. Syst. 7(2): 306-335 (2002) - [c8]Haitian Hu, David T. Blaauw, Vladimir Zolotov, Kaushik Gala, Min Zhao, Rajendran Panda, Sachin S. Sapatnekar:
A precorrected-FFT method for simulating on-chip inductance. ICCAD 2002: 221-227 - [c7]Min Zhao, Kaushik Gala, Vladimir Zolotov, Yuhong Fu, Rajendran Panda, R. Ramkumar, Bhuwan K. Agrawal:
Worst case clock skew under power supply variations. Timing Issues in the Specification and Synthesis of Digital Systems 2002: 22-28 - 2001
- [c6]Kaushik Gala, David T. Blaauw, Junfeng Wang, Vladimir Zolotov, Min Zhao:
Inductance 101: Analysis and Design Issues. DAC 2001: 329-334 - [c5]Min Zhao, Sachin S. Sapatnekar:
A New Structural Pattern Matching Algorithm for Technology Mapping. DAC 2001: 371-376 - 2000
- [j1]Min Zhao, Sachin S. Sapatnekar:
Timing-driven partitioning and timing optimization of mixedstatic-domino implementations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(11): 1322-1336 (2000) - [c4]Min Zhao, Rajendran Panda, Sachin S. Sapatnekar, Tim Edwards, Rajat Chaudhry, David T. Blaauw:
Hierarchical analysis of power distribution networks. DAC 2000: 150-155 - [c3]Min Zhao, Sachin S. Sapatnekar:
Dual-monotonic domino gate mapping and optimal output phase assignment of domino logic. ISCAS 2000: 309-312
1990 – 1999
- 1999
- [c2]Min Zhao, Sachin S. Sapatnekar:
Timing-driven partitioning for two-phase domino and mixed static/domino implementations. ICCAD 1999: 107-110 - 1998
- [c1]Min Zhao, Sachin S. Sapatnekar:
Technology mapping for domino logic. ICCAD 1998: 248-251
Coauthor Index
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