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2010 – 2019
- 2013
[j9]Tzung-Han Wu, Hsiang-Hui Chang, Shin-Fu Chen, Chinq-Shiun Chiu, Li-Shin Lai, Chi-Hsueh Wang, Song-Yu Yang, Ta-Hsin Lin, Jhy-Rong Chen, Hung-Chieh Tsai, Chi-Yao Yu, Sheng-Yuan Su, Tai-Yuan Yu, Chieh-Chuan Chin, Guang-Kaai Dehng, Augusto Marques, Caiyi Wang, George Chien:
A 65-nm GSM/GPRS/EDGE SoC With Integrated BT/FM. IEEE J. Solid State Circuits 48(5): 1161-1173 (2013)- 2011
- [j8]Chi-Yao Yu, Ivan Siu-Chuang Lu, Yen-Horng Chen, Lan-chou Cho, Chih-hao Eric Sun, Chih-Chun Tang, Hsiang-Hui Chang, Wen-Chang Lee, Sheng-Jui Huang, Tzung-Han Wu, Chinq-Shiun Chiu, George Chien:
A SAW-Less GSM/GPRS/EDGE Receiver Embedded in 65-nm SoC. IEEE J. Solid State Circuits 46(12): 3047-3060 (2011) - [c6]Lan-Chou Cho, Hsiang-Hui Chang, Augusto Marques, Albert Yang, Chinq-Shiun Chiu, Guang-Kaai Dehng:
A 1.22/6.7 ppm/°C VCO with frequency-drifting compensator in 60 nm CMOS. A-SSCC 2011: 101-104
2000 – 2009
- 2009
- [j7]Ping-Ying Wang, Jing-Hong Conan Zhan, Hsiang-Hui Chang, Hsiu-Ming (Sherman) Chang:
A Digital Intensive Fractional-N PLL and All-Digital Self-Calibration Schemes. IEEE J. Solid State Circuits 44(8): 2182-2192 (2009) - 2008
- [c5]Ping-Ying Wang, Jing-Hong Conan Zhan, Hsiang-Hui Chang, Bing-Yu Hsieh:
An analog enhanced all digtial RF fractional-N PLL with self-calibrated capability. CICC 2008: 749-752 - [c4]Ping-Ying Wang, Hsiang-Hui Chang, Jing-Hong Conan Zhan:
A fractional spur reduction technique for RF TDC-based all digital PLLs. ESSCIRC 2008: 422-425 - [c3]Hsiang-Hui Chang, Ping-Ying Wang, Jing-Hong Conan Zhan, Bing-Yu Hsieh:
A Fractional Spur-Free ADPLL with Loop-Gain Calibration and Phase-Noise Cancellation for GSM/GPRS/EDGE. ISSCC 2008: 200-201 - 2006
- [j6]Hsiang-Hui Chang, Jung-Yu Chang, Chun-Yi Kuo, Shen-Iuan Liu:
A 0.7-2-GHz self-calibrated multiphase delay-locked loop. IEEE J. Solid State Circuits 41(5): 1051-1061 (2006) - 2005
- [j5]Hsiang-Hui Chang, Shen-Iuan Liu:
A wide-range and fast-locking all-digital cycle-controlled delay-locked loop. IEEE J. Solid State Circuits 40(3): 661-670 (2005) - 2004
- [j4]Hsiang-Hui Chang, Rong-Jyi Yang, Shen-Iuan Liu:
Low jitter and multirate clock and data recovery circuit using a MSADLL for chip-to-chip interconnection. IEEE Trans. Circuits Syst. I Regul. Pap. 51-I(12): 2356-2364 (2004) - 2003
- [j3]Hsiang-Hui Chang, Jyh-Woei Lin, Shen-Iuan Liu:
A fast locking and low jitter delay-locked loop using DHDL. IEEE J. Solid State Circuits 38(2): 343-346 (2003) - [j2]Hsiang-Hui Chang, I-Hui Hua, Shen-Iuan Liu:
A spread-spectrum clock generator with triangular modulation. IEEE J. Solid State Circuits 38(4): 673-676 (2003) - [c2]Hsiang-Hui Chang, Shang-Ping Chen, Shen-Iuan Liu:
A shifted-averaging VCO with precise multiphase outputs and low jitter operation. ESSCIRC 2003: 647-650 - 2002
- [j1]Hsiang-Hui Chang, Jyh-Woei Lin, Ching-Yuan Yang, Shen-Iuan Liu:
A wide-range delay-locked loop with a fixed latency of one clock cycle. IEEE J. Solid State Circuits 37(8): 1021-1027 (2002) - [c1]Hsiang-Hui Chang, Jyh-Woei Lin, Shen-Iuan Liu:
A 6 MHz-130 MHz DLL with a fixed latency of one clock cycle delay. CICC 2002: 49-52
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