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ORCIDRimantas Seinauskas
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- affiliation: Kaunas University of Technology, Kaunas, Lithuania
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2010 – 2019
- 2018
[j11]Eduardas Bareisa, Vacius Jusas
, Kestutis Motiejunas, Liudas Motiejunas, Rimantas Seinauskas:
Black box delay fault models for non-scan sequential circuits. Comput. Sci. Inf. Syst. 15(1): 237-256 (2018)- 2015
- [j10]Eduardas Bareisa, Vacius Jusas, Kestutis Motiejunas, Rimantas Seinauskas:
Path delay test generation at functional level. IET Comput. Digit. Tech. 9(3): 135-141 (2015) - 2013
- [j9]Eduardas Bareisa, Vacius Jusas, Kestutis Motiejunas, Rimantas Seinauskas:
Functional delay test generation approach using a software prototype of the circuit. Comput. Sci. Inf. Syst. 10(3): 1165-1184 (2013) - [j8]Eduardas Bareisa, Vacius Jusas, Kestutis Motiejunas, Rimantas Seinauskas:
Delay fault testing using partial multiple scan chains. Microelectron. Reliab. 53(12): 2070-2077 (2013) - 2012
- [j7]Eduardas Bareisa, Vacius Jusas, Kestutis Motiejunas, Rimantas Seinauskas:
Evaluation of testability enhancement using software prototype. IET Comput. Digit. Tech. 6(3): 166-172 (2012) - 2011
- [j6]Eduardas Bareisa, Vacius Jusas, Kestutis Motiejunas, Rimantas Seinauskas:
Functional fault models for non-scan sequential circuits. Microelectron. Reliab. 51(12): 2402-2411 (2011)
2000 – 2009
- 2009
- [j5]Eduardas Bareisa, Vacius Jusas, Kestutis Motiejunas, Rimantas Seinauskas:
Functional delay test generation based on software prototype. Microelectron. Reliab. 49(12): 1578-1585 (2009) - 2008
- [j4]Eduardas Bareisa, Vacius Jusas, Kestutis Motiejunas, Rimantas Seinauskas:
Test generation at the algorithm-level for gate-level fault coverage. Microelectron. Reliab. 48(7): 1093-1101 (2008) - [c7]Eduardas Bareisa, Vacius Jusas, Kestutis Motiejunas, Rimantas Seinauskas:
Development of Functional Delay Tests. DSD 2008: 626-632 - 2007
- [j3]Eduardas Bareisa, Vacius Jusas, Kestutis Motiejunas, Rimantas Seinauskas:
Functional Test Generation Based on Combined Random and Deterministic Search Methods. Informatica 18(1): 3-26 (2007) - [c6]Eduardas Bareisa, Vacius Jusas, Kestutis Motiejunas, Rimantas Seinauskas:
Transition Faults Testing Based on Functional Delay Tests. DDECS 2007: 371-376 - [c5]Eduardas Bareisa, Vacius Jusas, Kestutis Motiejunas, Rimantas Seinauskas:
The Criteria of Functional Delay Test Quality Assessment. DSD 2007: 207-214 - 2006
- [c4]Eduardas Bareisa, Vacius Jusas, Kestutis Motiejunas, Rimantas Seinauskas:
Transition Fault Test Reuse. DSD 2006: 323-330 - 2005
- [j2]Eduardas Bareisa, Vacius Jusas, Kestutis Motiejunas, Rimantas Seinauskas:
The Realization-Independent Testing Based on the Black Box Fault Models. Informatica 16(1): 19-36 (2005) - [c3]Eduardas Bareisa, Vacius Jusas, Kestutis Motiejunas, Rimantas Seinauskas:
Functional Test Generation Remote Tool. DSD 2005: 192-195 - 2003
- [j1]Eduardas Bareisa, Kestutis Motiejunas, Rimantas Seinauskas:
Identifying Legal and Illegal States in Synchronous Sequential Circuits Using Test Generation. Informatica 14(2): 135-154 (2003) - 2001
- [c2]Vacius Jusas, Kestutis Paulikas, Rimantas Seinauskas:
Procedures for Selection of Validation Vectors on the Algorithm Level. LATW 2001: 90-95
1990 – 1999
- 1997
- [c1]Rimantas Seinauskas:
A distance laboratory for computer-aided design. MSE 1997: 107-108
Coauthor Index
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