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ORCID10th DDECS 2007: Kraków, Poland
- Patrick Girard, Andrzej Krasniewski, Elena Gramatová, Adam Pawlak, Tomasz Garbolino:
Proceedings of the 10th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2007), Kraków, Poland, April 11-13, 2007. IEEE Computer Society 2007, ISBN 1-4244-1161-0
Invited Presentations
- Daniel D. Gajski:
New Strategies for System-Level Design. 15 - Krishnendu Chakrabarty
:
Design and Test of Microfluidic Biochips. 17 - Janusz Rajski:
Logic Diagnosis and Yield Learning. 19
Session I: Design for Test & Defect Analysis
- Marco Bucci, Raimondo Luzzi:
A Testable Random Bit Generator Based on a High Resolution Phase Noise Detection. 23-28 - Jiri Jenícek, Ondrej Novák:
Test Pattern Compression Based on Pattern Overlapping. 29-34 - Maksim Jenihhin, Jaan Raik, Raimund Ubar, Witold A. Pleskacz, Michal Rakowski:
Layout to Logic Defect Analysis for Hierarchical Test Generation. 35-40
Session II: SOC Design & Test
- Bartosz Wojciechowski, Tomasz Kowalczyk, Wojciech Sakowski:
Design Platform for Quick Integration of an Internet Connectivity into System-on-Chips. 43-48 - Radoslaw Czarnecki, Stanislaw Deniziak:
Resource Constrained Co-synthesis of Self-reconfigurable SOPCs. 49-54 - Paolo Bernardi, Letícia Maria Veiras Bolzani, Matteo Sonza Reorda:
Extended Fault Detection Techniques for Systems-on-Chip. 55-60 - Anders Larsson, Erik Larsson, Petru Eles, Zebo Peng:
A Heuristic for Concurrent SOC Test Scheduling with Compression and Sharing. 61-66
Session III: Fault Analysis & Circuit Reliability
- Saibal Mukhopadhyay, Qikai Chen, Kaushik Roy:
Memories in Scaled Technologies: A Review of Process Induced Failures, Test Methodologies, and Fault Tolerance. 69-74 - Benoît Godard, Jean Michel Daga, Lionel Torres, Gilles Sassatelli:
Architecture for Highly Reliable Embedded Flash Memories. 75-80 - Zhicheng Liang, Makoto Ikeda, Kunihiro Asada:
Analysis of Noise Margins Due to Device Parameter Variations in Sub-100nm CMOS Technology. 81-86 - Maria Gkatziani, Rohit Kapur, Qing Su, Ben Mathew, Roberto Mattiuzzo, Laura Tarantini, Cy Hay, Salvatore Talluto, Thomas W. Williams:
Accurately Determining Bridging Defects from Layout. 87-90
Session IV: FPGA-Based Design
- Ernest Jamro, Maciej Wielgosz, Kazimierz Wiatr:
FPGA Implementation of Strongly Parallel Histogram Equalization. 93-98 - Grzegorz Borowik, Bogdan J. Falkowski, Tadeusz Luba:
Cost-Efficient Synthesis for Sequential Circuits Implemented Using Embedded Memory Blocks of FPGAs. 99-104 - Ari Kulmala, Erno Salminen, Timo D. Hämäläinen:
Instruction Memory Architecture Evaluation on Multiprocessor FPGA MPEG-4 Encoder. 105-110
Poster Session I
- Dongsoo Kim, Gunhee Han:
A Low Noise and Low Power CMOS Image Sensor with Pixel-level Correlated Double Sampling. 113-116 - Valeria Sipala, Domenico Lo Presti, Nunzio Randazzo, Luigi Caponetto:
A PMT Interface for the Optical Module Front-end of a Neutrino Underwater Telescope. 117-120 - Santiago de Pablo, Santiago Cáceres, Jesús A. Cebrián, Manuel Berrocal:
A Proposal for ASM++ Diagrams. 121-124 - Piotr Buciak, Jakub Botwicz:
Lightweight Multi-threaded Network Processor Core in FPGA. 125-130 - Jim Tørresen, Thor Arne Lovland:
Parts Obsolescence Challenges for the Electronics Industry. 131-134 - Khalil Arshak, Francis Adepoju, Essa Jafer:
Simulation and Characterization of Wireless Data Acquisition RF Systems for Medical Diagnostic Application. 135-138 - Ireneusz Brzozowski, Andrzej Kos:
Two-level Logic Synthesis for Low Power Based on New Model of Power Dissipation. 139-144 - Gurgen Harutunyan, Valery A. Vardanian, Yervant Zorian:
A March-based Fault Location Algorithm with Partial and Full Diagnosis for All Simple Static Faults in Random Access Memories. 145-148 - Tomasz Garbolino, Krzysztof Gucwa, Michal Kopec, Andrzej Hlawiczka:
Avoiding Crosstalk Influence on Interconnect Delay Fault Testing. 149-152 - Daniel Tille, Görschwin Fey, Rolf Drechsler:
Instance Generation for SAT-based ATPG. 153-156 - Khalil Arshak, Essa Jafer, Christian Ibala:
Power Testing of an FPGA-based System Using Modelsim Code Coverage Capability. 157-160 - Ajoy Kumar Palit, Kishore K. Duganapalli, Walter Anheier:
XSIM: An Efficient Crosstalk Simulator for Analysis and Modeling of Signal Integrity Faults in Both Defective and Defect-free Interconnects. 161-164
Session V: Memory Testing
- Prashant Dubey, Akhil Garg, Sravan Kumar Bhaskarani:
Built in Defect Prognosis for Embedded Memories. 167-172 - Luigi Dilillo, Bashir M. Al-Hashimi:
March CRF: an Efficient Test for Complex Read Faults in SRAM Memories. 173-178 - Zaid Al-Ars, Said Hamdioui, Georgi Gaydadjiev:
Manifestation of Precharge Faults in High Speed DRAM Devices. 179-184 - Philipp Öhler, Sybille Hellebrand, Hans-Joachim Wunderlich:
Analyzing Test and Repair Times for 2D Integrated Memory Built-in Test and Repair. 185-190
Session VI: Logic Design
- Peter Malík, Marcel Baláz, Tomás Pikula, Martin Simlastík:
An Improved MDCT IP Core Generator with Architectural Model Simulation. 193-198 - Chiou-Kou Tung, Yu-Cherng Hung, Shao-Hui Shieh, Guo-Shing Huang:
A Low-Power High-Speed Hybrid CMOS Full Adder for Embedded System. 199-202 - Tomás Martínek, Otto Fucík, Patrik Beck, Matej Lexa:
Automatic Generation of Circuits for Approximate String Matching. 203-208
Poster Session II
- Costin Cepisca, Sorin Dan Grigorescu, Mircea Covrig, Horia Andrei:
About the Efficiency of Real Time Sequences FFT Computing. 211-214 - Martin Simlastík, Viera Stopjaková, Libor Majer, Peter Malík:
Clockless Implementation of LEON2 for Low-Power Applications. 215-218 - Edward Hrynkiewicz, Stefan Kolodzinski:
Decomposition of Logic Functions in Reed-Muller Spectral Domain. 219-222 - Alexandru Amaricai, Mircea Vladutiu, Lucian Prodan, Mihai Udrescu, Oana Boncalo:
Design of Addition and Multiplication Units for High Performance Interval Arithmetic Processor. 223-226 - Jim Tørresen, Jorgen Norendal, Kyrre Glette:
Establishing a New Course in Reconfigurable Logic System Design. 227-230 - Artur L. Sobczyk, Arkadiusz W. Luczyk, Witold A. Pleskacz:
Power Dissipation in Basic Global Clock Distribution Networks. 231-234 - Roman P. Bazylevych, Ihor Podolskyy, Lubov Bazylevych:
Partitioning Optimization by Recursive Moves of Hierarchically Built Clusters. 235-238 - Alexandre Rousset, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel:
A Mixed Approach for Unified Logic Diagnosis. 239-242 - Lukás Sekanina:
Design and Analysis of a New Self-Testing Adder which Utilizes Polymorphic Gates. 243-246 - Mohammad Hossein Neishaburi, Mohammad Reza Kakoee, Masoud Daneshtalab, Saeed Safari, Zainalabedin Navabi:
A HW/SW Architecture to Reduce the Effects of Soft-Errors in Real-Time Operating System Services. 247-250 - Sergei B. Musin, Alexander A. Ivaniuk, Vyacheslav N. Yarmolik:
Multiple Errors Detection Technique for RAM. 251-254 - Tomasz Rudnicki, Andrzej Hlawiczka:
Test Pattern Generator for Delay Faults. 255-258
Session VII: Fault Tolerance I
- Oscar Ruano, Pilar Reyes, Juan Antonio Maestro, Luca Sterpone, Pedro Reviriego:
An Experimental Analysis of SEU Sensitiveness on System Knowledge-based Hardening Techniques. 261-266 - Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre:
A Novel Parity Bit Scheme for SBox in AES Circuits. 267-271
Session VIII: Analog & RF Design
- Dariusz Koscielnik, Marek Miskowicz:
Designing Time-to-Digital Converter for Asynchronous ADCs. 275-280 - Lukas Ruckay, Jiri Nedved:
Algorithm for DRM Signal Recognition in Time Domain and Hardware Realization. 281-286 - Vytautas Dumbrava, Linas Svilainis:
RF Transformer Model Parameters Measurement. 287-291
Session IX: Fault Tolerance II
- Jorge Semião, Judit Freijedo, Juan J. Rodríguez-Andina, Fabian Vargas, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira:
Improving Tolerance to Power-Supply and Temperature Variations in Synchronous Circuits. 295-300 - Manuel G. Gericota, Luís F. Lemos, Gustavo R. Alves, José M. Ferreira:
A Framework for Self-Healing Radiation-Tolerant Implementations on Reconfigurable FPGAs. 301-306 - René Kothe, Heinrich Theodor Vierhaus:
Flip-Flops and Scan-Path Elements for Nanoelectronics. 307-312 - Pawel Pawlowski, Adam Dabrowski, Mario Schölzel:
Proposal of VLIW Architecture for Application Specific Processors with Built-in-Self-Repair Facility via Variable Accuracy Arithmetic. 313-318
Poster Session III
- Pawel Russek, Kazimierz Wiatr:
Dedicated Architecture for Double Precision Matrix Multiplication in Supercomputing Environment. 321-324 - András Timár, Márta Rencz:
Design Issues of a Low Frequency Low-Pass Filter for Medical Applications Using CMOS Technology. 325-328 - Vladimir Havel, Karel K. Vlcek:
Feasibility of Image Compression in FPGA-based Neural Networks. 329-332 - Antti Rasmus, Ari Kulmala, Erno Salminen, Timo D. Hämäläinen:
IP Integration Overhead Analysis in System-on-Chip Video Encoder. 333-336 - Ábel Vámos:
Quadrature-Phase Topology of a High Frequency Ring Oscillator. 337-340 - Rung-Bin Lin, Da-Wei Hsu, Ming-Hsine Kuo, Meng-Chiou Wu:
Reticle Exposure Plans for Multi-Project Wafers. 341-344 - Gyula Bakonyi-Kiss, Zoltán Szucs:
Low Cost, Low Power, Intelligent Brake Temperature Sensor System for Automotive Applications. 345-348 - Matthias Bucher, Antonios Bazigos, Wladyslaw Grabinski:
Determining MOSFET Parameters in Moderate Inversion. 349-352 - Tomasz Golonek, Damian Grzechca, Jerzy Rutkowski:
Evolutionary System for Analog Test Frequencies Selection with Fuzzy Initialization. DDECS 2007: 353-356 - Pavel Kubalík, Jirí Kvasnicka, Hana Kubátová:
Fault Injection and Simulation for Fault Tolerant Reconfigurable Duplex System. 357-360 - Jan Korenek, Petr Kobierský:
Intrusion Detection System Intended for Multigigabit Networks. 361-364 - Wlodzimierz Jonca:
Open Defects Caused by Scratches and Yield Modelling in Deep Sub-micron Integrated Circuit. 365-368
Session X: Test Quality & Test Generation
- Eduardas Bareisa, Vacius Jusas, Kestutis Motiejunas, Rimantas Seinauskas:
Transition Faults Testing Based on Functional Delay Tests. 371-376 - Aristides Efthymiou:
Redundancy and Test-Pattern Generation for Asynchronous Quasi-Delay-Insensitive Combinational Circuits. 377-382 - Yann Oddos, Katell Morin-Allory, Dominique Borrione:
Prototyping Generators for On-line Test Vector Generation Based on PSL Properties. 383-388
Session XI: Model Checking & Debugging
- Marc Herbstritt, Bernd Becker, Erika Ábrahám, Christian Herde:
On Variable Selection in SAT-LP-based Bounded Model Checking of Linear Hybrid Automata. 391-396 - Fabrício Vivas Andrade, Márcia C. M. Oliveira, Antônio Otávio Fernandes, Claudionor José Nunes Coelho Jr.:
SAT-Based Equivalence Checking Based on Circuit Partitioning and Special Approaches for Conflict Clause Reuse. 397-402 - Frank Rogin, Erhard Fehlauer, Christian Haufe, Sebastian Ohnewald:
Debug Patterns for Efficient High-level SystemC Debugging. 403-408
Session XII: Analog & MEMS testing
- Thomas O. Shea, Ian Andrew Grout, Jeffrey Ryan:
Memory Based Analogue Signal Generation Implementation Issues for BIST. 411-416 - Petr Struhovský, Ondrej Subrt, Jirí Hospodka, Pravoslav Martínek:
Developing Virtual ADC Testing Environment in MAPLE. 417-422 - Zbigniew Piatek, Jerzy F. Kolodziejski, Witold A. Pleskacz:
ESD Failures of Integrated Circuits and Their Diagnostics Using Transmission Line Pulsing. 423-428 - János Mizsei, M. Reggente:
MEMS Testing by Vibrating Capacitor. 429-432
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