default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDICCD 1989: Cambridge, MA, USA
- Computer Design: VLSI in Computers and Processors, ICCD 1989. Proceedings., 1989 IEEE International Conference on, Cambridge, MA, USA, October 2-4, 1989. IEEE 1989, ISBN 0-8186-1971-6
- D. Spaderna, P. Green, K. Tam, T. Datta, M. Kumar:
An integrated floating point vector processor for DSP and scientific computing. 8-13 - Ross A. W. Smith, Gerald E. Sobelman, George Luk, Koichi Suda, Jeff Bracken:
FPC: a floating-point processor controller chip for systolic signal processing. 14-17 - Çetin Kaya Koç
:
A fast algorithm for mixed-radix conversion in residue arithmetic. 18-21 - David J. Chen, Ji-Chien Lee, Bing J. Sheu:
SLAM: a smart analog module layout generator for mixed analog-digital VLSI design. 24-27 - Donald Curry:
Schematic specification of datapath layout. 28-34 - Gabriele Saucier, Régis Leveugle, Pierre Abouzeid:
A channelless layout for multilevel synthesis with compiled cells. 35-38 - Srinivas Patil, Sudhakar M. Reddy:
A test generation system for path delay faults. 40-43 - Tracy Larrabee:
A framework for evaluating test pattern generation strategies. 44-47 - W. B. Zeng, D. Z. Wei:
Intelligent backtracking in test generation for combinational circuits. 48-51 - C. G. Lin-Hendel, W. J. Bertram, M. S. Dhanaliwala, R. J. Pimpinella, J. M. Segelken, King L. Tai:
Integrated optoelectronics-to-VLSI packaging technology. 54-57 - Brewster O. Kahle, Edward C. Parish, Thomas A. Lane, Jerry A. Quam:
Optical interconnects for interprocessor communications in the Connection Machine. 58-61 - Alex G. Dickinson, Michael E. Prise:
An integrated free space optical bus. 62-65 - Yang-Tung Huang, Raymond K. Kostuk:
A low-impedance load detector circuit for optical interconnects. 66-71 - H. Dijkstra, Gerben Essink, A. J. M. Hafkamp, H. den Hengst, C. M. Huizer, Arthur H. M. van Roermund, Robert J. Sluyter, P. J. Snijder:
A general-purpose video signal processor: architecture and programming. 74-77 - Gilles Privat, Marc Renaudin:
Motion estimation VLSI architecture for image coding. 78-81 - Stewart G. Smith, Ralph W. Morgan, Julian G. Payne:
Generic ASIC architecture for digital signal processing. 82-85 - Sailesh K. Rao:
The matrix transform chip. 86-89 - Alexander Herrigel, M. Glaser, Wolfgang Fichtner:
A global floorplanning technique for VLSI layout. 92-95 - Michael C. McFarland:
A fast floor planning algorithm for architectural evaluation. 96-99 - Massoud Pedram, Bryan Preas:
Accurate prediction of physical design characteristics for random logic. 100-108 - Sunil Arvindam, Vipin Kumar, V. Nageshwara Rao:
Floorplan optimization on multiprocessors. 109-114 - Sandip Kundu, Sudhakar M. Reddy:
Design of TSC checkers for implementation in CMOS technology. 116-119 - Niraj K. Jha:
Design of sufficiently strongly self-checking embedded checkers for systematic and separable codes. 120-123 - Régis Leveugle, Gabriele Saucier:
Concurrent checking in dedicated controllers. 124-127 - L. G. Chen, T. H. Chen:
Computation with simultaneously concurrent error detection using bi-directional operands. 128-131 - Randy D. Groves, Richard R. Oehler:
An IBM second generation RISC processor architecture. 134-137 - H. B. Bakoglu, Gregory F. Grohoski, L. E. Thatcher, James A. Kahle, Charles R. Moore, David P. Tuttle, Warren E. Maule, W. R. Hardell Jr., Dwain A. Hicks, M. Nguyenphu, Robert K. Montoye, W. T. Glover, Sudhir Dhawan:
IBM second-generation RISC machine organization. 138-142 - Paul Villarrubia, Gary Nusbaum, Robert Masleid, P. T. Patel:
IBM RISC chip design methodology. 143-147 - Shiwei Wang, Yarsun Hsu, C. J. Tan:
A novel message switch for highly parallel systems. 150-155 - Christopher Bucci, Alexander Albicki:
An algorithm for voice and data integration on packet-switched local area networks. 156-159 - James W. Dolter, Parmesh Ramanathan, Kang G. Shin:
A microprogrammable VLSI routing controller for HARTS. 160-163 - Nasir Darwish, Bella Bose:
Efficient double asymmetric error correcting codes. 166-171 - Horng-Dar Lin, David G. Messerschmitt:
High throughput reconstruction of Huffman-coded images. 172-175 - Joseph R. Cavallaro, Christopher D. Near, M. Ümit Uyar:
Fault-tolerant VLSI processor array for the SVD. 176-180 - Beatrice Fu, Avtar Saini, Patrick P. Gelsinger:
Performance and microarchitecture of the i486TM processor. 182-187 - James Miller, Ben Roberts, Paul Madland:
High performance circuits for the i486TM processor. 188-192 - Ed Grochowski, Ken Shoemaker:
Issues in the implementation of the i486TM cache and bus. 193-198 - Pat Gelsinger, Sundar Iyengar, Joseph Krauskopf, James Nadir:
Computer aided design and built in self test on the i486TM CPU. 199-202 - Paul Loewenstein:
Formal verification of state-machines using higher-order logic. 204-207 - Jerry R. Burch:
Modeling timing assumptions with trace theory. 208-211 - David L. Dill, Steven M. Nowick, Robert F. Sproull:
Automatic verification of speed-independent circuits with Petri net specifications. 212-216 - Soumitra Bose, Allan L. Fisher:
Verifying pipelined hardware using symbolic logic simulation. 217-221 - C. G. Lin-Hendel, L. H. Cong:
The design of a multi-chip single package digital signal processing module. 224-228 - Norman P. Jouppi:
Integration and packaging plateaus of processor performance. 229-232 - Ravi Kaw:
Comparison of chip crossing delay in various packaging environments. 233-236 - Jerzy W. Rozenblit, John L. Prince, Olgierd A. Palusinski, T. D. Whipple:
Computer aided design system for VLSI interconnections. 237-241 - Dick L. Liu, Rajesh Galivanche, Charlie C. Hsu:
An automatic test pattern generation program for large ASICs. 244-248 - Jeffrey R. Fox, Douglas Pastorello:
The role of synthesis in an ASIC design environment. 249-254 - Glen S. Miranker, Jon Rubinstein, John Sanguinetti:
Evolution in the application of ASICs in the second-generation Titan. 255-259 - Maciej J. Ciesielski, Saeyang Yang, Marek A. Perkowski:
Multiple-valued Boolean minimization based on graph coloring. 262-265 - P. Lammens, Luc J. M. Claesen, Hugo De Man:
Correctness verification of VLSI modules supported by a very efficient Boolean prover. 266-269 - Chin-Long Wey, Sin-Min Chang, Jing-Yang Jou:
OPAM: an efficient output phase assignment for multilevel logic minimization. 270-273 - Y.-H. Shih, S. M. Kang:
Fast MOS circuit simulation with a direct equation solver. 276-279 - Jeffrey C. Bier, Edward A. Lee:
Frigg: a simulation environment for multiple-processor DSP system development. 280-283 - Eduard Cerny, John P. Hayes, Nicholas C. Rumin:
Magnitude classes in switch-level modeling. 284-288 - Mohan Harihara, Prem R. Menon:
Identification of undetectable faults in combinational circuits. 290-293 - Steven P. Smith:
An enhanced high performance combinational fault simulator using two-way parallelism. 294-297 - Daniel G. Saab, Ibrahim N. Hajj, Joseph T. Rahmeh:
Parallel-concurrent fault simulation. 298-301 - H. Klose, B. Zehner, A. Wieder:
BiCMOS, a technology for high-speed/high-density ICs. 304-309 - P. Kuen Fung, Hiep V. Tran, David B. Scott:
Impact of BiCMOS technology on SRAM circuit design. 310-313 - Gerard Boudon, Frank Wallart, Eric Maillart:
Internal ECL-BiCMOS translator circuits in half micron technology. 314-317 - Hideo Maejima, Tadaaki Bandoh, Yoji Nishio, Tadashi Fukushima, Masanori Odaka, Atsuo Hotta:
Circuit technologies for BiCMOS VLSI's as computer elements. 318-321 - S. Muroga, X. Q. Xiang, J. Limqueco, L. P. Lin, K. C. Chen:
A logic network synthesis system, SYLON. 324-328 - Pierre G. Paulin, Franck J. Poirot:
Logic decomposition algorithms for the timing optimization of multi-level logic. 329-333 - P. A. Subrahmanyam:
Automated synthesis of systems with interacting asynchronous (self-timed) and synchronous components. 334-337 - Brian R. Bannister, David R. Melton, Gaynor E. Taylor:
Testability of digital circuits via the spectral domain. 340-343 - Anita Gleason, Wen-Ben Jone:
Hamming count-a compaction testing technique. 344-347 - V. Bobin, D. Radhakrishnan:
A VLSI residue arithmetic multiplier with fault detection capability. 348-351 - Silvia Ercolani, Michele Favalli, Maurizio Damiani, Piero Olivo, Bruno Riccò:
Improved testability evaluations in combinational logic networks. 352-355 - Yasuhiro Nakatsuka, Takashi Hotta, Shigeya Tanaka, Tadaaki Bandoh, Ryuichi Satomura, Syuichi Nakagami, Tetsuo Nakano, Atsuo Hotta, Takashi Moriyama, Shigemi Adachi, Shoji Iwamoto:
A high performance BiCMOS 32-bit microprocessor. 358-361 - Nobuhiro Tomabechi:
Counter-based residue arithmetic circuit for easily testable VLSI digital signal processing systems. 362-365 - Paul Y. Lu, Kevin Dawallu:
A VLSI module for IEEE floating-point multiplication/division/square root. 366-368 - Amar Mukherjee, N. Ranganathan, Mostafa A. Bassiouni:
Adaptive and pipelined VLSI designs for tree-based codes. 369-372 - Hon P. Sit, Monica Rosenrauch Nofal, Sunhyuk Kimn:
An 80 MFLOPS floating-point engine in the Intel i860(TM) processor. 374-379 - Michael W. Rhodehamel:
The bus interface and paging units of the i860TM microprocessor. 380-384 - Piyush Patel, Diane Douglass:
Architectural features of the i860(TM)-microprocessor RISC core and on-chip caches. 385-390 - C. Leonard Berman:
Ordered binary decision diagrams and circuit structure. 392-395 - Abdul A. Malik, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
Logic minimization for factored forms. 396-399 - Bill Lin, A. Richard Newton:
A generalized approach to the constrained cubical embedding problem. 400-403 - Toru Shimizu, Shunichi Iwata, Yuichi Saito, Toyohiko Yoshida, Masahito Matsuo, Junichi Hinata, Kazunori Saito:
A 32-bit microprocessor with high performance bit-map manipulation instructions. 406-409 - M. D. Asal, J. D. Keay, A. M. Fellows, I. C. Robertson, N. K. Ing-Simmons, I. J. Sherlock:
Novel architecture for a high performance full custom graphics processor. 410-414 - Masayoshi Tachibana, Yoshihisa Kondo, Yasuo Yamada, Masafumi Takahashi, Haruyuki Tago:
High performance I/O processors for real-time pulse handling. 415-418 - Chia-Jeng Tseng, Steven G. Rothweiler, Shailesh Sutarwala, Ajit M. Prabhu:
Mind: a module binder for high level synthesis. 420-423 - Hyunchul Shin, Nam Sung Woo:
A cost function based optimization technique for scheduling in data path synthesis. 424-427 - Vijay K. Raj:
DAGAR: an automatic pipelined microarchitecture synthesis system. 428-431 - Chi-Min Chu, Miodrag Potkonjak, Markus Thaler, Jan M. Rabaey:
HYPER: an interactive synthesis environment for high performance real time applications. 432-435 - Chenming Hu:
Reliability issues of MOS and bipolar ICs. 438-442 - Bruno Ciciani, Giuseppe Iazeolla:
A yield model for the evaluation of topologically constrained chip architectures. 443-446 - Farid N. Najm, Ibrahim N. Hajj, Ping Yang:
Electromigration median time-to-failure based on a stochastic current waveform. 447-450 - Calvin J. A. Hsia, C. Y. Roger Chen:
On a class of (2n-1)-stage rearrangeable interconnection networks. 452-455 - Chung-Han Chen, Laxmi N. Bhuyan:
A systolic approach to multistage interconnection network design. 456-459 - Vijay K. Jain, David L. Landis, C. E. Alvarez:
Systolic L-U decomposition array with a new reciprocal cell. 460-465 - Gregory L. Frazier, Yuval Tamir:
The design and implementation of a multi-queue buffer for VLSI communication switches. 466-471 - Wayne D. Dettloff, Kathy E. Yount, Hiroyuki Watanabe:
A fuzzy logic controller with reconfigurable, cascadable architecture. 474-478 - Mohammad Zubair, B. B. Madan:
Systolic implementation of neural networks. 479-482 - J. Ouali, Gabriele Saucier:
A flexible architecture for neural networks. 483-486 - Frank Warkowski, Jens Leenstra, Jos Nijhuis, Lambert Spaanenburg:
Issues in the test of artificial neural networks. 487-490 - Yusuf Leblebici, Sung-Mo Kang:
Simulation of MOS circuit performance degradation with emphasis on VLSI design-for-reliability. 492-495 - Wen-Jay Hsu, Bing J. Sheu, Vance C. Tyree:
Digital and analog integrated-circuit design with built-in reliability. 496-499 - Yi-Chieh Chang, Kang G. Shin:
A module-sliced approach for high yield VLSI/WSI processors. 500-503 - William C. Hobart Jr., Harvey G. Cragon:
Locality characteristics of symbolic programs. 508-511 - Umakishore Ramachandran, M. Yousef Amin Khalidi:
A design of a memory management unit for object-based systems. 512-517 - Michael M. Hsieh, Tek C. Wei, William Van Loo:
A cached system architecture dedicated for the system IO activity on a CPU board. 518-522 - Xiao-Ming Xiong, Dan Green, John Hardin, Lawrence Riedel:
Automatic signal net-matching for VLSI layout design. 524-527 - Pierre-François Dubois:
The channel intersection problem in the building block style layout. 528-531 - A. A. J. de Lange, J. S. J. de Lange, J. F. Vink:
A hierarchical constraint graph generation and compaction system for symbolic layout. 532-535 - Alexander Herrigel, J. Kamm, Wolfgang Fichtner:
Macrocell-level compaction with automatic jog introduction. 536-539 - Miron Abramovici, J. W. Bierbauer, R. H. Hellman, C. L. Hong, David T. Miller, R. G. Taylor:
System-level design verification in the AT&T computer division: overview and strategy. 542-547 - Miron Abramovici, James J. Kulikowski, David T. Miller, Prem R. Menon:
System-level design verification in the AT&T Computer Division: tools. 548-554 - Quinn Canfield, Paul Barford, Paul Kinzelman, Cary Trlica:
A system simulation environment within Digital. 555-560 - Gwan Choi, Ravi K. Iyer, Victor Carreno:
FOCUS: an experimental environment for validation of fault-tolerant systems - case study of a jet-engine controller. 561-564 - John Y. Sayah, Charles R. Kime:
Scheduling unequal length tests in high performance VLSI system implementations. 566-570 - Ravinder S. Shergill, Pak-Ho Yeung, Patrick A. Tucci:
Built-in test methodology for a full custom processor chip. 571-575 - Chien-In Henry Chen, Gerald E. Sobelman:
An efficient approach to pseudo-exhaustive test generation for BIST design. 576-579 - Yervant Zorian, Najmi Jarwala:
Designing fault-tolerant, testable, VLSI processors using the IEEE P1149.1 boundary-scan architecture. 580-584
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2025-05-22 00:24 CEST by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
