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ORCIDPriyank Kalla
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2020 – today
- 2023
[c48]Bhavani Sampathkumar, Bailey Martin, Ritaja Das, Priyank Kalla, Florian Enescu
:
Logic Synthesis from Polynomials with Coefficients in the Field of Rationals. ISMVL 2023: 82-87- [c47]Pratishtha Agnihotri, Lawrence M. Schlitt, Priyank Kalla, Steve Blair:
Abstractions for Modeling the Effects of Wall Surface Roughness in Silicon Photonic Microring Resonators. LATS 2023: 1-6 - 2021
- [c46]Vikas Rao, Haden Ondricek, Priyank Kalla, Florian Enescu:
Rectification of Integer Arithmetic Circuits using Computer Algebra Techniques. ICCD 2021: 186-195 - [c45]Vikas Rao, Irina Ilioaea, Haden Ondricek, Priyank Kalla, Florian Enescu:
Word-Level Multi-Fix Rectifiability of Finite Field Arithmetic Circuits. ISQED 2021: 41-47 - [c44]Vikas Rao, Haden Ondricek, Priyank Kalla, Florian Enescu:
Algebraic Techniques for Rectification of Finite Field Circuits. VLSI-SoC 2021: 1-6
2010 – 2019
- 2019
- [j11]Utkarsh Gupta, Priyank Kalla, Vikas Rao:
Boolean Gröbner Basis Reductions on Finite Field Datapath Circuits Using the Unate Cube Set Algebra. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(3): 576-588 (2019) - [c43]Utkarsh Gupta, Priyank Kalla, Irina Ilioaea, Florian Enescu:
Exploring Algebraic Interpolants for Rectification of Finite Field Arithmetic Circuits with Gröbner Bases. ETS 2019: 1-6 - 2018
- [c42]Vikas Rao, Utkarsh Gupta, Irina Ilioaea, Arpitha Srinath, Priyank Kalla, Florian Enescu:
Post-Verification Debugging and Rectification of Finite Field Arithmetic Circuits using Computer Algebra Techniques. FMCAD 2018: 1-9 - [c41]Utkarsh Gupta, Irina Ilioaea, Vikas Rao, Arpitha Srinath, Priyank Kalla, Florian Enescu:
On the Rectifiability of Arithmetic Circuits using Craig Interpolants in Finite Fields. VLSI-SoC 2018: 49-54 - [c40]Utkarsh Gupta, Irina Ilioaea, Vikas Rao, Arpitha Srinath, Priyank Kalla, Florian Enescu:
Rectification of Arithmetic Circuits with Craig Interpolants in Finite Fields. VLSI-SoC (Selected Papers) 2018: 79-106 - [p1]Robert Wille, Krishnendu Chakrabarty, Rolf Drechsler, Priyank Kalla:
Emerging Circuit Technologies: An Overview on the Next Generation of Circuits. Advanced Logic Synthesis 2018: 43-67 - 2016
- [j10]Tim Pruss, Priyank Kalla, Florian Enescu:
Efficient Symbolic Computation for Word-Level Abstraction From Combinational Circuits for Verification Over Finite Fields. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(7): 1206-1218 (2016) - [c39]Xiaojun Sun, Irina Ilioaea, Priyank Kalla, Florian Enescu:
Finding Unsatisfiable Cores of a Set of Polynomials Using the Gröbner Basis Algorithm. CP 2016: 859-875 - [c38]Xiaojun Sun, Priyank Kalla, Florian Enescu:
Word-level traversal of finite state machines using algebraic geometry. HLDVT 2016: 142-149 - [c37]Lawrence M. Schlitt, Priyank Kalla, Steve Blair:
A Methodology for Thermal Characterization Abstraction of Integrated Opto-Electronic Layouts. VLSID 2016: 270-275 - 2015
- [c36]Xiaojun Sun, Priyank Kalla, Tim Pruss, Florian Enescu:
Formal verification of sequential Galois field arithmetic circuits using algebraic geometry. DATE 2015: 1623-1628 - [c35]Priyank Kalla:
Formal Verification of Arithmetic Datapaths using Algebraic Geometry and Symbolic Computation. FMCAD 2015: 2 - [c34]Miodrag Potkonjak, Deming Chen, Priyank Kalla, Steven P. Levitan:
DA Vision 2015: From Here to Eternity. ICCAD 2015: 271-277 - 2014
- [j9]Christopher Condrat, Priyank Kalla, Steve Blair:
Crossing-Aware Channel Routing for Integrated Optics. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(6): 814-825 (2014) - [c33]Tim Pruss, Priyank Kalla, Florian Enescu:
Equivalence Verification of Large Galois Field Arithmetic Circuits using Word-Level Abstraction via Gröbner Bases. DAC 2014: 152:1-152:6 - [c32]Christopher Condrat, Priyank Kalla, Steve Blair:
Thermal-aware synthesis of integrated photonic ring resonators. ICCAD 2014: 557-564 - 2013
- [j8]Jinpeng Lv, Priyank Kalla, Florian Enescu:
Efficient Gröbner Basis Reductions for Formal Verification of Galois Field Arithmetic Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(9): 1409-1420 (2013) - [c31]Christopher Condrat, Priyank Kalla, Steve Blair:
Crossing-aware channel routing for photonic waveguides. MWSCAS 2013: 649-652 - [c30]Christopher Condrat, Priyank Kalla, Steve Blair:
Channel routing for integrated optics. SLIP 2013: 1-8 - 2012
- [c29]Jinpeng Lv, Priyank Kalla, Florian Enescu:
Efficient Gröbner basis reductions for formal verification of galois field multipliers. DATE 2012: 899-904 - [c28]Christopher Condrat, Priyank Kalla, Steve Blair:
A methodology for physical design automation for integrated optics. MWSCAS 2012: 598-601 - [c27]Jinpeng Lv, Priyank Kalla:
Formal Verification of Galois Field Multipliers Using Computer Algebra Techniques. VLSI Design 2012: 388-393 - 2011
- [c26]Christopher Condrat, Priyank Kalla, Steve Blair:
Logic synthesis for integrated optics. ACM Great Lakes Symposium on VLSI 2011: 13-18 - [c25]Jinpeng Lv, Priyank Kalla, Florian Enescu:
Verification of composite Galois field multipliers over GF ((2m)n) using computer algebra techniques. HLDVT 2011: 136-143
2000 – 2009
- 2009
- [j7]Sivaram Gopalakrishnan, Priyank Kalla:
2009 ACM TODAES best paper award: Optimization of polynomial datapaths using finite ring algebra. ACM Trans. Design Autom. Electr. Syst. 14(4): 47:1 (2009) - [c24]Sivaram Gopalakrishnan, Priyank Kalla:
Algebraic techniques to enhance common sub-expression elimination for polynomial system synthesis. DATE 2009: 1452-1457 - [c23]Priyank Kalla, Prabhat Mishra:
Chairs' welcome message. HLDVT 2009: 1 - 2008
- [j6]Namrata Shekhar, Priyank Kalla, M. Brandon Meredith, Florian Enescu:
Simulation Bounds for Equivalence Verification of Polynomial Datapaths Using Finite Ring Algebra. IEEE Trans. Very Large Scale Integr. Syst. 16(4): 376-387 (2008) - [c22]Neal Tew, Priyank Kalla, Namrata Shekhar, Sivaram Gopalakrishnan:
Verification of arithmetic datapaths using polynomial function models and congruence solving. ICCAD 2008: 122-128 - 2007
- [j5]Sivaram Gopalakrishnan, Priyank Kalla:
Optimization of polynomial datapaths using finite ring algebra. ACM Trans. Design Autom. Electr. Syst. 12(4): 49 (2007) - [c21]Sivaram Gopalakrishnan, Priyank Kalla, Florian Enescu:
Optimization of Arithmetic Datapaths with Finite Word-Length Operands. ASP-DAC 2007: 511-516 - [c20]Sivaram Gopalakrishnan, Priyank Kalla, M. Brandon Meredith, Florian Enescu:
Finding linear building-blocks for RTL synthesis of polynomial datapaths with fixed-size bit-vectors. ICCAD 2007: 143-148 - [c19]Christopher Condrat, Priyank Kalla:
A Gröbner Basis Approach to CNF-Formulae Preprocessing. TACAS 2007: 618-631 - 2006
- [j4]Maciej J. Ciesielski, Priyank Kalla, Serkan Askar:
Taylor Expansion Diagrams: A Canonical Representation for Verification of Data Flow Designs. IEEE Trans. Computers 55(9): 1188-1201 (2006) - [c18]Namrata Shekhar, Priyank Kalla, Florian Enescu:
Equivalence verification of arithmetic datapaths with multiple word-length operands. DATE 2006: 824-829 - [c17]Namrata Shekhar, Priyank Kalla, M. Brandon Meredith, Florian Enescu:
Simulation Bounds for Equivalence Verification of Arithmetic Datapaths with Finite Word-Length Operands. FMCAD 2006: 179-186 - [c16]Vijay Durairaj, Priyank Kalla:
Guiding CNF-SAT Search by Analyzing Constraint-Variable Dependencies and Clause Lengths. HLDVT 2006: 155-161 - 2005
- [c15]Namrata Shekhar, Priyank Kalla, Florian Enescu, Sivaram Gopalakrishnan:
Equivalence verification of polynomial datapaths with fixed-size bit-vectors using finite ring algebra. ICCAD 2005: 291-296 - [c14]Namrata Shekhar, Priyank Kalla, Sivaram Gopalakrishnan, Florian Enescu:
Exploiting Vanishing Polynomials for Equivalence Veri.cation of Fixed-Size Arithmetic Datapaths. ICCD 2005: 215-220 - [c13]Vijay Durairaj, Priyank Kalla:
Variable Ordering for Efficient SAT Search by Analyzing Constraint-Variable Dependencies. SAT 2005: 415-422 - 2004
- [c12]Vijay Durairaj, Priyank Kalla:
Dynamic analysis of constraint-variable dependencies to guide SAT diagnosis. HLDVT 2004: 135-140 - [c11]Vijay Durairaj, Priyank Kalla:
Exploiting hypergraph partitioning for efficient Boolean satisfiability. HLDVT 2004: 141-146 - [c10]Vijay Durairaj, Priyank Kalla:
Guiding CNF-SAT search via efficient constraint partitioning. ICCAD 2004: 498-501 - 2003
- [c9]Sivaram Gopalakrishnan, Vijay Durairaj, Priyank Kalla:
Integrating CNF and BDD based SAT solvers. HLDVT 2003: 51-56 - 2002
- [j3]Priyank Kalla, Maciej J. Ciesielski:
A comprehensive approach to the partial scan problem using implicitstate enumeration. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(7): 810-826 (2002) - [j2]Navin Vemuri, Priyank Kalla, Russell Tessier:
BDD-based logic synthesis for LUT-based FPGAs. ACM Trans. Design Autom. Electr. Syst. 7(4): 501-525 (2002) - [c8]Maciej J. Ciesielski, Priyank Kalla, Zhihong Zeng, Bruno Rouzeyre:
Taylor Expansion Diagrams: A Compact, Canonical Representation with Applications to Symbolic Verification. DATE 2002: 285-289 - [c7]Priyank Kalla, Maciej J. Ciesielski, Emmanuel Boutillon, Eric Martin:
High-level design verification using Taylor Expansion Diagrams: first results. HLDVT 2002: 13-17 - 2001
- [j1]Priyank Kalla, Zhihong Zeng, Maciej J. Ciesielski:
Strategies for solving the Boolean satisfiability problem using binary decision diagrams. J. Syst. Archit. 47(6): 491-503 (2001) - [c6]Zhihong Zeng, Priyank Kalla, Maciej J. Ciesielski:
LPSAT: a unified approach to RTL satisfiability. DATE 2001: 398-402 - [c5]Maciej J. Ciesielski, Priyank Kalla, Zhihong Zeng, Bruno Rouzeyre:
Taylor expansion diagrams: a new representation for RTL verification. HLDVT 2001: 70-75 - 2000
- [c4]Priyank Kalla, Zhihong Zeng, Maciej J. Ciesielski, ChiLai Huang:
A BDD-Based Satisfiability Infrastructure Using the Unate Recursive Paradigm. DATE 2000: 232-236
1990 – 1999
- 1999
- [c3]Priyank Kalla, Maciej J. Ciesielski:
Performance Driven Resynthesis by Exploiting Retiming-Induced State Register Equivalence. DATE 1999: 638-642 - 1998
- [c2]Priyank Kalla, Maciej J. Ciesielski:
A comprehensive approach to the partial scan problem using implicit state enumeration. ITC 1998: 651-657 - 1997
- [c1]Priyank Kalla, Maciej J. Ciesielski:
Testability of Sequential Circuits with Multi-Cycle False Path. VTS 1997: 322-328
Coauthor Index
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