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ORCIDISCAS 1994: London, UK - Volume 1
- 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30 - June 2, 1994. IEEE 1994, ISBN 0-7803-1916-8
CAD 1: Simulation & Systolic Analysis
- Jai-Cheol Lee, Yu Hen Hu:
EDLICS: A New Relaxation-Based Electrical Circuit Simulation Technique. 1-4 - Takeshi Senoo, Hiroaki Makino, Hideki Asai:
Relaxation-Based Steady-State Analysis of Single- and Multi-Conductor Transmission Lines in Frequency Domain. 5-8 - Masakatsu Nishigaki, Nobuyuki Tanaka, Hideki Asai:
Mixed Mode Circuit Simulator SPLIT2.1 using Dynamic Network Separation and Selective Trace. 9-12 - Abdolreza Nabavi-Lishi, Nicholas C. Rumin:
Inverter-based Models for Current Analysis of CMOS Logic Circuits. 13-16 - Krzysztof Zamlynski, Jan Ogrodzki:
Electro-Thermal Analysis of IC's. 17-20 - Shyh-Jye Jou, Mei-Fang Perng, Chauchin Su, C. K. Wang:
Hierarchical Techniques for Symbolic Analysis of Large Electronic Circuits. 21-24 - Francisco V. Fernández, Piet Wambacq, Georges G. E. Gielen
, Ángel Rodríguez-Vázquez, Willy M. C. Sansen:
Symbolic Analysis of Large Analog Integrated Circuits by Approximation During Expression Generation. 25-28 - Scott E. Greenfield, Marwan M. Hassoun:
Direct Hierarchical Symbolic Transient Analysis of Linear Circuits. 29-32 - Wlodzimierz M. Zuberek, Agnieszka Konczykowska, D. Martin:
An Approach to Integrated Numerical & Symbolic Circuit Analysis. 33-36
CAD 2: Datapath Synthesis
- Ching-Chuen Jong, Y. Y. H. Lam, S. S. Lim, T. S. Teng:
Time-Zone: A New Algorithm for Register Allocation in Data Path Synthesis. 37-40 - N. A. Ramakrishna, Magdy A. Bayoumi:
Storage Allocation Strategies for Data Path Synthesis of ACICs. 41-44 - Jer-Min Jou, Ren-Der Chen, Shiann-Rong Kuang:
Multiport Memory Based Data Path Allocation Focusing on Interconnection Optimization. 45-48 - Kwangsoo Seo, Jeongyop Lee, Moonkey Lee:
Allocation of Multiport Memories in ASIC Data Path Synthesis. 49-52 - Bruce A. Johnston, Peter J. W. Graumann, Laurence E. Turner:
DSP System Synthesis Including Variable Data Path Width. 53-56 - Yuan Hu, Bradley S. Carlson:
A Unified Algorithm for Estimation and Scheduling in Data Path Synthesis. 57-60 - Santanu Dutta, Sudip Nag, Kaushik Roy:
ASAP: A Transistor Sizing Tool for Speed Area and Power Optimization of Static CMOS Circuits. 61-64 - Naim Ben-Hamida, Bozena Kaminska:
High Level Synthesis with Testability Constraints. 65-68
CAD 3: POSTER - Layout, Thermal & Test
- Shujian Zhang, Rod Byrne, Jon C. Muzio, D. Michael Miller:
Why Cellular Automata are better than LFSRs as Built-in Self-test Generators for Sequential-type Faults. 69-72 - Akachai Sang-In, Peter Y. K. Cheung:
A Method of Representative Fault Selection in Digital Circuits for ATPG. 73-76 - Beom-Ik Cheon, Walter Anheier, Rainer Laur:
A New Strategy for Test Pattern Generation in Sequential Circuits. 77-80 - Cristiana Bolchini, Franco Fummi, Donatella Sciuto:
Two-Dimensional Sequential Array Architectures: Design for Testability Approaches. 81-84 - Jer-Min Jou, Shung-Chih Chen, Ren-Der Chen:
A Super Fast & Memory Efficient Diagnostic Simulation Algorithm for Combinatorial Circuits. 85-88 - Mokhtar Hirech, Olivier Florent, Alain Greiner, El Housseine Rejouan:
A Redefinable Symbolic Simulation Technique to Testability Design Rules Checking. 89-92 - Mineo Kaneko, Kazuhiro Sakaguchi:
Oscillation Fault Diagnosis for Analog Circuits based on Boundary Search with Perturbation Model. 93-96 - Mariusz Ziólko:
Optimal Placement of Heat Dissipating Elements. 97-99 - H. Mauritz, Wolfgang Mathis:
Integration System as Adaptive Control System. 101-104 - Jin-Tai Yan, Pei-Yung Hsiao:
Region Definition of Minimizing the Number of Switchboxes and Ordering Assignment. 105-108 - N. S. Nagaraj, Paul Krivacek, Mark Harward:
Approximate Computation of Signal Characteristics of On-chip RC Interconnect Trees. 109-112 - Joseph L. Ganley, James P. Cohoon:
Routing a Multi-Terminal Critical Net: Steiner Tree Construction in the Presence of Obstacles. 113-116 - Dilvan de Abreu Moreira, Les T. Walczowski:
Automated Placement for a Leaf Cell Generator. 117-120
CAD 4: Statistical Design
- Ming Qu, M. A. Styblinski:
Statistical Characterization and Modeling of Analog Functional Blocks. 121-124 - Jin-Qin Lu, Kimihiro Ogawa, Takehiko Adachi, Andrzej J. Strojwas:
Stochastic Interpolation Model Scheme for Statistical Circuit Design. 125-128 - John W. Bandler, S. H. Chen, R. M. Biernacki, Kim Halskov Madsen:
The Huber Concept in Device Modeling, Circuit Diagnosis and Design Centering. 129-132 - Hua Su, Christopher Michael, Mohammed Ismail:
Statistical Constrained Optimization of Analog CMOS Circuits using Empirical Performance Models. 133-136 - Leszek J. Opalski, Jacek Wojciechowski:
Application of the Piecewise Ellipsoidal Approximation Technique to Design Centering. 137-140 - Morie E. Malowany, Gordon W. Roberts, Vinod K. Agarwal:
VAMP: A Hierarchical Framework for Design for Manufacturability. 141-144 - John W. Bandler, R. M. Biernacki, S. H. Chen, P. A. Grobelny:
A CAD Environment for Performance and Yield Driven Circuit Design Employing Electromagnetic Field Simulators. 145-148 - Syed A. Aftab, M. A. Styblinski:
IC Variability Minimization using a New Cp and Cpk Based Variability/Performance Measure. 149-152 - J. C. Zhang:
Worst Case Design of Digital Integrated Circuits. 153-156
CAD 5: Placement
- Abdelhakim Safir, Baher Haroun, Krishnaiyan Thulasiraman:
A Floorplanner driven by Structural & Timing Constraints. 157-160 - Cheng-Hsi Chen, Ioannis G. Tollis:
A New Approach to Floorplan Area Optimization: To Slice or not to Slice? 161-164 - Tetsushi Koide, Yoshinori Katsura, Katsumi Yamatani, Shin'ichi Wakabayashi, Noriyoshi Yoshida:
A Floorplanning Method with Topological Constraint Manipulation. 165-168 - P. Chin, Anthony Vannelli:
Interior Point Methods for Placement. 169-172 - Achim G. Hoffmann:
The Dynamic Locking Heuristic - A New Graph Partitioning Algorithm. 173-176 - Carsten F. Ball, Peter V. Kraus, Dieter A. Mlynski:
Fuzzy Partitioning applied to VLSI-Floorplanning and Placement. 177-180 - M. Kemal Unaltuna, Vijay Pitchumani:
A Stochastic Reward & Punishment Neural Network Algorithm for Circuit Bipartitioning. 181-184 - Masahiko Toyonaga, Shih-Tsung Yang, Toshiro Akino, Isao Shirakawa:
A New Approach of Fractional-Dimension Based Module Clustering for VLSI Layout. 185-188 - Yhonkyong Choi, Juhyun Lee, Chong S. Rim:
Automatic Functional Cell Generation in the Sea-of-Gates Layout Style. 189-192
CAD 6: POSTERS - Synthesis & DSP CAD
- Masaki Hashizume, Takeomi Tamesada, Akio Sakamoto:
A Maximum Clique Derivation Algorithm for Simplification of Incompletely Specified Machines. 193-196 - Bogdan J. Falkowski, Chip-Hong Chang:
Efficient Algorithms for the Calculation of Arithmetic Spectrum from OBDD & Synthesis of OBDD from Arithmetic Spectrum for Incompletely Specified Boolean Functions. 197-200 - Stanislaw Deniziak, Krzysztof Sapiecha:
Cupland - A Behavioral Level Description Compiler for Designing of PLD/EPLD-Based Systems. 201-204 - Uwe F. Baake, Sorin A. Huss:
Scheduling of Signal Transition Graphs under Timing Constraints. 205-208 - Jazi Eko Istiyanto, Sean Monaghan:
FPGA-Memory Tradeoff in the High-Level Synthesis of FPGA-Based Reconfigurable Systems. 209-212 - Sanjive Agarwala, Patrick W. Bosshart:
A Linear Time Algorithm for Timing Directed Circuit Optimizations. 213-216 - Chris J. Rousse, Alison J. Carter:
Exploring Delay/Area Trade-Offs of an LDI Filter Using a Natural Based Algorithm. 217-220 - Kunihiro Fujiyoshi, Yoji Kajitani, Hiroshi Niitsu:
Design of Optimum Totally Perfect Connection-Blocks of FPGA. 221-224 - Shin'ichi Wakabayashi, Kazunori Isomoto, Tetsushi Koide, Noriyoshi Yoshida:
A Systolic Graph Partitioning Algorithm for VLSI Design. 225-228 - Michael F. Dossis, James M. Noras, Gary J. Porter:
Synthesis of Customized Hardware from ADA. 229-232 - M. J. M. Heijiligers, H. A. Hilderink, Adwin H. Timmer, Jochen A. G. Jess:
NEAT: An Object Oriented High-Level Synthesis Interface. 233-236 - Ning Song, Malgorzata Chrzanowska-Jeske:
Output Column Folding for Cellular-Architecture FPGAs. 237-240 - Giuseppe Caruso:
An Improved Algorithm for Boolean Factoring. 241-244 - Karim Khordoc, Eduard Cerny:
Modeling Cell Processing Hardware with Action Diagrams. 245-248 - Minjoong Rim, Rajiv Jain:
Estimating Performance Characteristics of Loop Transformations. 249-252 - William Y. M. Lai, C. K. Tse, C. H. Szeto:
Computer Formulation of Averaged Models for Periodically-Switched Networks. 253-256 - Jukka Lahti:
Graphical Specification Methods for Digital Telecommuniation ASICs. 257-260 - Tolga Çiloglu, Zafer Ünver:
A Novel Method for Discrete Coefficient FIR Digital Filter Design. 261-264 - Jouni Isoaho, Jari Nurmi:
An Overall FIR Filter Optimization Tool for High Granularity Implementation Technologies. 265-268
CAD 7: FORUM - Mixed Analog-Digital Simulation
- John Harris, Mark Chadwick, Tom Quan, Norbert Diesing, Edward MacRobbie:
Mixed Analog-Digital Simulation: The tools are here... is anyone really using them? 269-274
CAD 8: Synthesis & Test
- Masahiro Fujita, Jerry Chih-Yuan Yang, Edmund M. Clarke, Xudong Zhao, Patrick C. McGeer:
Fast Spectrum Computation for Logic Functions using Binary Decision Diagrams. 275-278 - Loïc Vandeventer, Jean François Santucci:
Using Binary Decision Diagrams to Speed up the Test Pattern Generation of Behavioral Circuit Descriptions Written in Hardware Description Languages. 279-282 - Liang-Fang Chao, Edwin Hsing-Mean Sha:
Retiming and Clock Skew for Synchronous Systems. 283-286 - Chien-Chung Tsai, Malgorzata Marek-Sadowska:
Detecting Symmetric Variables in Boolean Functions using Generalized Reel-Muller Forms. 287-290 - Jérôme Fron, Jerry Chih-Yuan Yang, Maurizio Damiani, Giovanni De Micheli:
A Synthesis Framework Based on Trace and Automata Theory. 291-294 - Yuan Hu, Bradley S. Carlson:
Improved Lower Bounds for the Scheduling Optimization Problem. 295-298 - Gianpiero Cabodi, Paolo Camurati, Stefano Quer:
Detecting hard faults with combined approximate forward/backward symbolic techniques. 299-302 - João P. Marques Silva, Karem A. Sakallah:
Efficient and Robust Test Generation-Based Timing Analysis. 303-306 - Sung Tae Jung, Chu Shik Jhon:
Direct Synthesis of Efficient Speed-Independent Circuits from Deterministic Signal Transition Graphs. 307-310
CAD 9: Modeling & Simulation
- Robert Chen-Hao Chang, Bing J. Sheu:
An Analog MOS Model for Circuit Simulation and Benchmark Test Results. 311-314 - M. E. Kole, J. Smith, Otto E. Herrmann:
Modeling Symmetry in Analog Electronic Circuits. 315-318 - Dongfeng Zhao, Ray R. Chen:
GODPE: Global Optimization in Small Signal Device Model Parameter Extraction. 319-322 - Jack Lau, Ping K. Ko, Philip C. Chan:
On the Modelling of a CMOS Magnetic Sensor. 323-326 - Christophe Lallement, R. Bouchakour, T. Maurel:
A VDMOS transistor model taking into account the thermoelectrical interactions. 327-330 - David I. Long, Saad Sabih Ahmed Medhat:
Behavioural Modelling of Mixed Signal ASICs: A new multi-level approach. 331-334 - Ayman I. Kayssi, Karem A. Sakallah:
Macromodel Simplification Using Dimensional Analysis. 335-338 - Nicolas Moenclaey, Andreas Kaiser:
Accurate Modelling of the Non-Linear Settling Behaviour of Current Memory Circuits. 339-342 - Hans Georg Brachtendorf, Rainer Laur:
Modeling of Frequency-dependent Hysteresis with SPICE. 343-346
CAD 10: Analog CAD
- Zhihua Wang, Georges G. E. Gielen, Willy M. C. Sansen:
A Novel Method for the Fault Detection of Analog Integrated Circuits. 347-350 - Salman Ahmed, Peter Y. K. Cheung:
Analog Fault Diagnosis - A Practical Approach. 351-354 - Margherita Pillan, Donatella Sciuto:
Constraint Generation & Placement for Automatic Layout Design of Analog Integrated Circuits. 355-358 - K. K. Wee, R. J. Mack:
Towards Expandable and Generalised Analogue Design Automation. 359-362 - Ronald S. Gyurcsik, George Gad-El-Karim, Griff L. Bilbro:
Sensitivity-Driven Placement of Analog Modules. 363-366 - Jorge Chávez Orzáez, Antonio Jesús Torralba Silgado, Leopoldo García Franquelo:
A Fuzzy-logic based Tool for Topology Selection in Analog Synthesis. 367-370 - Nuno C. G. Horta, José E. Franca:
A Methodology for Automatic Generation of Data Conversion Topologies from Algorithms. 371-374 - Miguel Angel Aguirre Echánove, Jorge Chávez Orzáez, Antonio Jesús Torralba Silgado, Leopoldo García Franquelo:
Analog Design optimization by means of a Tabu Search Approach. 375-378
CAD 11: POSTER - Simulation, Modelling & Statistical Design
- Mustafa Çelik, Ogan Ocali, Mehmet Ali Tan, Abdullah Atalar:
Improving AWE Accuracy Using Multipoint Padé Approximation. 379-382 - Jan Ogrodzki, Dariusz Bukat:
Compact Modelling in Circuit Simulation: the General Purpose Analyser OPTIMA-3. 383-386 - Hans Peter Amann, Philippe Moeschler, Fausto Pellandini, Alain Vachoux, Charles Munk, Daniel Mlynek:
High-Level Specification of Behavioural Hardware Models with MODES. 387-390 - Mitiko Miura-Mattausch, Alexander Rahm, Michael Bollu, Ute Feldmann, Dominique Savignac:
A Novel Consistent MOSFET Model for CAD Application with Reduced Calculation Time. 391-394 - Hannu Jokinen, Martti Valtonen:
Small-Signal Analysis of Nonideal Switched-Capacitor Circuits. 395-398 - Erik Stoy, Zebo Peng:
An Integrated Modelling Technique for Hardware/Software Systems. 399-402 - Paul Van Halen:
A Physical Charge-Based Model for the Space Charge Region of Abrupt and Linear Semiconductor Junctions. 403-406 - Rahul B. Deokar, Sachin S. Sapatnekar:
A Graph-Theoretic Approach to Clock Skew Optimization. 407-410 - Masaki Ishida, Koichi Hayashi, Masakatsu Nishigaki, Hideki Asai:
Iterated Timing Analysis with Dynamic Partitioning Technique for Bipolar Transistor Circuits. 411-414 - Bengt-Arne Molin, Sven Mattisson:
Concurrent Switch-Level Timing Simulation Based on Waveform Relaxation. 415-418 - Vijaya Gopal Bandi, Hideki Asai:
Transient Simulation of Coupled Lossy Interconnects by Window Partitioning Technique. 419-422 - Ying-Wen Bai:
Interval Finite-Difference Methods for Digital MOS Circuits Simulation. 423-426 - Keng-Hua Shi, A. K. Jastrzebski, Les T. Walczowski, J. Barnaby:
A Multi-Mode Simulation System for GaAs Circuits. 427-430 - Kewei Yang, Richard C. Meitzler, Andreas G. Andreou:
A Model for MOS Effective Channel Mobility with Emphasis in the Subthreshold and Transition Region. 431-434 - Harish Kriplani, Farid N. Najm, Ibrahim N. Hajj:
Improved Delay and Current Models for Estimating Maximum Currents in CMOS VLSI Circuits. 435-438 - Luís Felipe Uebel, Sergio Bampi:
A Timing Model for VLSI CMOS Circuits Verification and Optimization. 439-442 - A. B. van der Wal, Robert G. J. Arendsen, Aarnout Brombacher, Otto E. Herrmann:
Hierarchical Statistical Verification of Large Full Custom CMOS Circuits. 443-446 - Hsiao-Dong Chiang, Chia-Chi Chu:
A Systematic Search Method for Obtaining Multiple Local Optimal Solutions of Nonlinear Programming Problems. 447-450
CAD 12: FORUM - Symbolic Analysis
- Francisco V. Fernández, Georges G. E. Gielen, Lawrence Huelsman, Agnieszka Konczykowska, Stefano Manetti, Willy M. C. Sansen, Jirí Vlach:
Pleasures, Perils and Pitfalls of Symbolic Analysis. 451-457
CAD 13: Routing
- Qi-Jun Zhang, Michel S. Nakhla:
Signal Integrity Analysis and Optimization of VLSI Interconnects using Neural Network Models. 459-462 - Todd D. Hodes, Bernard A. McCoy, Gabriel Robins:
Dynamically-Wiresized Elmore-Based Routing Constructions. 463-466 - Wasim Khan, Sreekrishna Madhwapathy, Naveed A. Sherwani:
A Hierarchical Approach to Clock Routing in High Performance Systems. 467-470 - T. W. Her, D. F. Wong:
Over-the-Cell Routing with Cell Orientations Consideration. 471-474 - Naresh Kumar Seghal, C. Y. Roger Chen, John M. Acken:
A High Performance General Purpose Multi-Point Signal Router. 475-478 - Ira Pramanick, Hyder Ali:
Analysis and Experiments for a Parallel Solution to the All Pairs Shortest Path Problem. 479-482 - Nozomu Togawa, Masao Sato, Tatsuo Ohtsuki:
A Simultaneous Placement and Global Routing Algorithm for FPGAs. 483-486 - Henning Spruth, Frank M. Johannes, Kurt Antreich:
PHIroute: A Parallel Hierarchical Sea-of-Gates Router. 487-490 - Juan A. Prieto, José M. Quintana, Adoración Rueda, José L. Huertas:
An Algorithm for the Place-and-Route Problem in the Layout of Analog Circuits. 491-494
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