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2020 – today
- 2024
[c79]Zdenek Vasícek:
Automated Synthesis of Commutative Approximate Arithmetic Operators. CEC 2024: 1-8- [c78]Zdenek Vasícek, Vojtech Mrazek, Lukás Sekanina:
Automated Verifiability-Driven Design of Approximate Circuits: Exploiting Error Analysis. DATE 2024: 1-6 - [c77]Jan Klhufek, Miroslav Safar, Vojtech Mrazek, Zdenek Vasícek, Lukás Sekanina:
Exploring Quantization and Mapping Synergy in Hardware-Aware Deep Neural Network Accelerators. DDECS 2024: 1-6 - [i11]Jan Klhufek, Miroslav Safar, Vojtech Mrazek, Zdenek Vasícek, Lukás Sekanina:
Exploring Quantization and Mapping Synergy in Hardware-Aware Deep Neural Network Accelerators. CoRR abs/2404.05368 (2024) - [i10]Vojtech Mrazek, Argyris Kokkinis, Panagiotis Papanikolaou, Zdenek Vasícek, Kostas Siozios, Georgios Tzimpragos, Mehdi Baradaran Tahoori, Georgios Zervakis:
Evolutionary Approximation of Ternary Neurons for On-sensor Printed Neural Networks. CoRR abs/2407.20589 (2024) - 2023
- [j16]Michal Pinos, Vojtech Mrazek
, Filip Vaverka, Zdenek Vasícek, Lukás Sekanina:
Acceleration Techniques for Automated Design of Approximate Convolutional Neural Networks. IEEE J. Emerg. Sel. Topics Circuits Syst. 13(1): 212-224 (2023) - [c76]Roman Kalkreuth, Zdenek Vasícek, Jakub Husa, Diederick Vermetten, Furong Ye, Thomas Bäck:
General Boolean Function Benchmark Suite. FOGA 2023: 84-95 - [c75]Roman Kalkreuth, Zdenek Vasícek, Jakub Husa, Diederick Vermetten, Furong Ye, Thomas Bäck:
Towards a General Boolean Function Benchmark Suite. GECCO Companion 2023: 591-594 - [c74]Bharath Srinivas Prabakaran, Vojtech Mrazek, Zdenek Vasícek, Lukás Sekanina, Muhammad Shafique:
Xel-FPGAs: An End-to-End Automated Exploration Framework for Approximate Accelerators in FPGA-Based Systems. ICCAD 2023: 1-9 - [e1]Gisele L. Pappa, Mario Giacobini, Zdenek Vasícek:
Genetic Programming - 26th European Conference, EuroGP 2023, Held as Part of EvoStar 2023, Brno, Czech Republic, April 12-14, 2023, Proceedings. Lecture Notes in Computer Science 13986, Springer 2023, ISBN 978-3-031-29572-0 [contents] - [i9]Bharath Srinivas Prabakaran, Vojtech Mrazek, Zdenek Vasícek, Lukás Sekanina, Muhammad Shafique:
autoXFPGAs: An End-to-End Automated Exploration Framework for Approximate Accelerators in FPGA-Based Systems. CoRR abs/2303.04734 (2023) - 2022
- [j15]Milan Ceska, Jirí Matyás, Vojtech Mrazek, Lukás Sekanina, Zdenek Vasícek, Tomás Vojnar:
SagTree: Towards efficient mutation in evolutionary circuit approximation. Swarm Evol. Comput. 69: 100986 (2022) - [c73]Roman Kalkreuth, Léo Françoso Dal Piccol Sotto, Zdenek Vasícek:
Graph-based genetic programming. GECCO Companion 2022: 958-982 - [c72]Jitka Kocnová, Zdenek Vasícek:
Delay-aware evolutionary optimization of digital circuits. ISVLSI 2022: 188-193 - 2021
- [j14]David Hodan, Vojtech Mrazek, Zdenek Vasícek:
Semantically-oriented mutation operator in cartesian genetic programming for evolutionary circuit design. Genet. Program. Evolvable Mach. 22(4): 539-572 (2021) - [c71]Zdenek Vasícek:
Synthesis of approximate circuits for LUT-based FPGAs. DDECS 2021: 17-22 - [c70]Jitka Kocnová, Zdenek Vasícek:
Resynthesis of logic circuits using machine learning and reconvergent paths. DSD 2021: 69-76 - 2020
- [j13]Milan Ceska, Jirí Matyás, Vojtech Mrazek, Lukás Sekanina, Zdenek Vasícek, Tomás Vojnar:
Adaptive verifiability-driven strategy for evolutionary approximation of arithmetic circuits. Appl. Soft Comput. 95: 106466 (2020) - [j12]Vojtech Mrazek, Lukás Sekanina, Zdenek Vasícek:
Libraries of Approximate Circuits: Automated Design and Application in CNN Accelerators. IEEE J. Emerg. Sel. Topics Circuits Syst. 10(4): 406-418 (2020) - [j11]Jitka Kocnová, Zdenek Vasícek:
EA-based resynthesis: an efficient tool for optimization of digital circuits. Genet. Program. Evolvable Mach. 21(3): 287-319 (2020) - [j10]Mohammad Saeed Ansari, Vojtech Mrazek, Bruce F. Cockburn, Lukás Sekanina, Zdenek Vasícek, Jie Han:
Improving the Accuracy and Hardware Efficiency of Neural Networks Using Approximate Multipliers. IEEE Trans. Very Large Scale Integr. Syst. 28(2): 317-328 (2020) - [c69]Vojtech Mrazek, Lukás Sekanina, Zdenek Vasícek:
Using Libraries of Approximate Circuits in Design of Hardware Accelerators of Deep Neural Networks. AICAS 2020: 243-247 - [c68]Bharath Srinivas Prabakaran, Vojtech Mrazek, Zdenek Vasícek, Lukás Sekanina, Muhammad Shafique:
ApproxFPGAs: Embracing ASIC-Based Approximate Arithmetic Components for FPGA-Based Systems. DAC 2020: 1-6 - [c67]Filip Vaverka, Vojtech Mrazek, Zdenek Vasícek, Lukás Sekanina:
TFApprox: Towards a Fast Emulation of DNN Approximate Hardware Accelerators on GPU. DATE 2020: 294-297 - [c66]Alberto Bosio, Stefano Di Carlo, Patrick Girard, Ernesto Sánchez, Alessandro Savino, Lukás Sekanina, Marcello Traiola, Zdenek Vasícek, Arnaud Virazel:
Design, Verification, Test and In-Field Implications of Approximate Computing Systems. ETS 2020: 1-10 - [c65]David Hodan, Vojtech Mrazek, Zdenek Vasícek:
Semantically-oriented mutation operator in cartesian genetic programming for evolutionary circuit design. GECCO 2020: 940-948 - [i8]Filip Vaverka, Vojtech Mrazek, Zdenek Vasícek, Lukás Sekanina:
TFApprox: Towards a Fast Emulation of DNN Approximate Hardware Accelerators on GPU. CoRR abs/2002.09481 (2020) - [i7]Milan Ceska, Jirí Matyás, Vojtech Mrazek, Lukás Sekanina, Zdenek Vasícek, Tomás Vojnar:
Adaptive Verifiability-Driven Strategy for Evolutionary Approximation of Arithmetic Circuits. CoRR abs/2003.02491 (2020) - [i6]Vojtech Mrazek, Lukás Sekanina, Zdenek Vasícek:
Using Libraries of Approximate Circuits in Design of Hardware Accelerators of Deep Neural Networks. CoRR abs/2004.10483 (2020) - [i5]Bharath Srinivas Prabakaran, Vojtech Mrazek, Zdenek Vasícek, Lukás Sekanina, Muhammad Shafique:
ApproxFPGAs: Embracing ASIC-Based Approximate Arithmetic Components for FPGA-Based Systems. CoRR abs/2004.10502 (2020) - [i4]David Hodan, Vojtech Mrazek, Zdenek Vasícek:
Semantically-Oriented Mutation Operator in Cartesian Genetic Programming for Evolutionary Circuit Design. CoRR abs/2004.11018 (2020)
2010 – 2019
- 2019
- [j9]Zdenek Vasícek:
Formal Methods for Exact Analysis of Approximate Circuits. IEEE Access 7: 177309-177331 (2019) - [c64]Vojtech Mrazek, Muhammad Abdullah Hanif, Zdenek Vasícek, Lukás Sekanina, Muhammad Shafique:
autoAx: An Automatic Design Space Exploration and Circuit Building Methodology utilizing Libraries of Approximate Components. DAC 2019: 123 - [c63]Zdenek Vasícek, Vojtech Mrazek, Lukás Sekanina:
Automated Circuit Approximation Method Driven by Data Distribution. DATE 2019: 96-101 - [c62]Jitka Kocnová, Zdenek Vasícek:
Towards a Scalable EA-Based Optimization of Digital Circuits. EuroGP 2019: 81-97 - [c61]Jitka Kocnová, Zdenek Vasícek:
Impact of subcircuit selection on the efficiency of CGP-based optimization of gate-level circuits. GECCO (Companion) 2019: 377-378 - [c60]Vojtech Mrazek, Zdenek Vasícek, Lukás Sekanina, Muhammad Abdullah Hanif, Muhammad Shafique:
ALWANN: Automatic Layer-Wise Approximation of Deep Neural Network Accelerators without Retraining. ICCAD 2019: 1-8 - [c59]Jitka Kocnová, Zdenek Vasícek:
EA-Based Refactoring of Mapped Logic Circuits. ISCAS 2019: 1-5 - [p3]Lukás Sekanina, Zdenek Vasícek, Vojtech Mrazek:
Automated Search-Based Functional Approximation for Digital Circuits. Approximate Circuits 2019: 175-203 - [i3]Vojtech Mrazek, Muhammad Abdullah Hanif, Zdenek Vasícek, Lukás Sekanina, Muhammad Shafique:
autoAx: An Automatic Design Space Exploration and Circuit Building Methodology utilizing Libraries of Approximate Components. CoRR abs/1902.10807 (2019) - [i2]Zdenek Vasícek, Vojtech Mrazek, Lukás Sekanina:
Automated Circuit Approximation Method Driven by Data Distribution. CoRR abs/1903.04188 (2019) - [i1]Vojtech Mrazek, Zdenek Vasícek, Lukás Sekanina, Muhammad Abdullah Hanif, Muhammad Shafique:
ALWANN: Automatic Layer-Wise Approximation of Deep Neural Network Accelerators without Retraining. CoRR abs/1907.07229 (2019) - 2018
- [j8]Vojtech Mrazek, Zdenek Vasícek, Radek Hrbacek:
Role of circuit representation in evolutionary design of energy-efficient approximate circuits. IET Comput. Digit. Tech. 12(4): 139-149 (2018) - [j7]Vojtech Mrazek, Zdenek Vasícek, Lukás Sekanina, Honglan Jiang, Jie Han:
Scalable Construction of Approximate Multipliers With Formally Guaranteed Worst Case Error. IEEE Trans. Very Large Scale Integr. Syst. 26(11): 2572-2576 (2018) - [c58]Vojtech Mrazek, Zdenek Vasícek, Lukás Sekanina:
Design of Quality-Configurable Approximate Multipliers Suitable for Dynamic Environment. AHS 2018: 264-271 - [c57]Milan Ceska, Jirí Matyás, Vojtech Mrazek, Lukás Sekanina, Zdenek Vasícek, Tomás Vojnar:
ADAC: Automated Design of Approximate Circuits. CAV (1) 2018: 612-620 - [c56]Vojtech Mrazek, Zdenek Vasícek:
Evolutionary design of large approximate adders optimized for various error criteria. GECCO (Companion) 2018: 294-295 - [c55]Vojtech Mrazek, Marek Sýs, Zdenek Vasícek, Lukás Sekanina, Vashek Matyas:
Evolving boolean functions for fast and efficient randomness testing. GECCO 2018: 1302-1309 - [c54]Lukás Sekanina, Vojtech Mrazek, Zdenek Vasícek:
Design Space Exploration for Approximate Implementations of Arithmetic Data Path Primitives. ICECS 2018: 377-380 - [c53]Lukás Sekanina, Zdenek Vasícek, Alberto Bosio, Marcello Traiola, Paolo Rech, Daniel Oliveira, Fernando Fernandes, Stefano Di Carlo:
Special session: How approximate computing impacts verification, test and reliability. VTS 2018: 1 - 2017
- [j6]Zdenek Vasícek, Vojtech Mrazek:
Trading between quality and non-functional properties of median filter in embedded systems. Genet. Program. Evolvable Mach. 18(1): 45-82 (2017) - [c52]Vojtech Mrazek, Radek Hrbacek, Zdenek Vasícek, Lukás Sekanina:
EvoApproxSb: Library of approximate adders and multipliers for circuit design and benchmarking of approximation methods. DATE 2017: 258-261 - [c51]Zdenek Vasícek, Vojtech Mrazek, Lukás Sekanina:
Towards low power approximate DCT architecture for HEVC standard. DATE 2017: 1576-1581 - [c50]Vojtech Mrazek, Zdenek Vasícek:
Parallel optimization of transistor level circuits using cartesian genetic programming. GECCO (Companion) 2017: 1849-1856 - [c49]Milan Ceska, Jirí Matyás, Vojtech Mrazek, Lukás Sekanina, Zdenek Vasícek, Tomás Vojnar:
Approximating complex arithmetic circuits with formal error guarantees: 32-bit multipliers accomplished. ICCAD 2017: 416-423 - [c48]Muhammad Shafique, Rehan Hafiz, Muhammad Usama Javed, Sarmad Abbas, Lukás Sekanina, Zdenek Vasícek, Vojtech Mrazek:
Adaptive and Energy-Efficient Architectures for Machine Learning: Challenges, Opportunities, and Research Roadmap. ISVLSI 2017: 627-632 - 2016
- [j5]Zdenek Vasícek, Lukás Sekanina:
Evolutionary design of complex approximate combinational circuits. Genet. Program. Evolvable Mach. 17(2): 169-192 (2016) - [c47]Radek Hrbacek, Vojtech Mrazek, Zdenek Vasícek:
Automatic design of approximate circuits by means of multi-objective evolutionary algorithms. DTIS 2016: 1-6 - [c46]Zdenek Vasícek, Lukás Sekanina:
Search-based synthesis of approximate circuits implemented into FPGAs. FPL 2016: 1-4 - [c45]Vojtech Mrazek, Syed Shakib Sarwar, Lukás Sekanina, Zdenek Vasícek, Kaushik Roy:
Design of power-efficient approximate multipliers for approximate artificial neural networks. ICCAD 2016: 81 - [c44]Vojtech Mrazek, Zdenek Vasícek:
Automatic design of arbitrary-size approximate sorting networks with error guarantee. PATMOS 2016: 221-228 - [c43]Zdenek Vasícek, Vojtech Mrazek, Lukás Sekanina:
Evolutionary functional approximation of circuits implemented into FPGAs. SSCI 2016: 1-8 - 2015
- [j4]Zdenek Vasícek, Lukás Sekanina:
Evolutionary Approach to Approximate Digital Circuits Design. IEEE Trans. Evol. Comput. 19(3): 432-444 (2015) - [c42]Vojtech Mrazek, Zdenek Vasícek:
Automatic Design of Low-Power VLSI Circuits: Accurate and Approximate Multipliers. EUC 2015: 106-113 - [c41]Vojtech Mrazek, Zdenek Vasícek:
Evolutionary Design of Transistor Level Digital Circuits Using Discrete Simulation. EuroGP 2015: 66-77 - [c40]Zdenek Vasícek:
Cartesian GP in Optimization of Combinational Circuits with Hundreds of Inputs and Thousands of Gates. EuroGP 2015: 139-150 - [c39]Zdenek Vasícek, Lukás Sekanina:
Circuit Approximation Using Single- and Multi-objective Cartesian GP. EuroGP 2015: 217-229 - [c38]Vojtech Mrazek, Zdenek Vasícek, Lukás Sekanina:
Evolutionary Approximation of Software for Embedded Systems: Median Function. GECCO (Companion) 2015: 795-801 - [c37]Zdenek Vasícek, Lukás Sekanina:
Evolutionary Approximation of Complex Digital Circuits. GECCO (Companion) 2015: 1505-1506 - [p2]Lukás Sekanina, Zdenek Vasícek:
Functional Equivalence Checking for Evolution of Complex Digital Circuits. Evolvable Hardware 2015: 175-189 - 2014
- [c36]Lukás Sekanina, Zdenek Vasícek:
On Evolutionary Approximation of Logic Circuits. Computing with New Resources 2014: 367-378 - [c35]Lukás Sekanina, Ondrej Ptak, Zdenek Vasícek:
Cartesian genetic programming as local optimizer of logic networks. IEEE Congress on Evolutionary Computation 2014: 2901-2908 - [c34]Zdenek Vasícek, Lukás Sekanina:
Evolutionary design of approximate multipliers under different error metrics. DDECS 2014: 135-140 - [c33]Zdenek Vasícek, Michal Bidlo:
On Evolution of Multi-category Pattern Classifiers Suitable for Embedded Systems. EuroGP 2014: 234-245 - [c32]Vojtech Mrazek, Zdenek Vasícek:
Acceleration of transistor-level evolution using Xilinx Zynq Platform. ICES 2014: 9-16 - [c31]Zdenek Vasícek, Lukás Sekanina:
How to evolve complex combinational circuits from scratch? ICES 2014: 133-140 - 2013
- [j3]Lukás Sekanina, Richard Ruzicka, Zdenek Vasícek, Václav Simek, Petr Hanácek:
Implementing A Unique Chip Id On A Reconfigurable Polymorphic Circuit. Inf. Technol. Control. 42(1): 7-14 (2013) - [j2]Zdenek Vasícek, Michal Bidlo, Lukás Sekanina:
Evolution of efficient real-time non-linear image filters for FPGAs. Soft Comput. 17(11): 2163-2180 (2013) - [c30]Michal Bidlo, Zdenek Vasícek:
Evolution of cellular automata with conditionally matching rules. IEEE Congress on Evolutionary Computation 2013: 1178-1185 - [c29]Lukás Sekanina, Zdenek Vasícek:
Approximate circuit design by means of evolvable hardware. ICES 2013: 21-28 - [c28]Michal Bidlo, Zdenek Vasícek:
Functional-level development of image filters by means of cellular automata. ICES 2013: 29-36 - 2012
- [b1]Zdenek Vasícek:
Acceleration Methods for Evolutionary Design of Digital Circuits. Brno University of Technology, Czech Republic, 2012 - [c27]Michal Bidlo, Zdenek Vasícek:
Cellular Automaton as Sorting Network Generator Using Instruction-Based Development. ACRI 2012: 214-223 - [c26]Michal Bidlo, Zdenek Vasícek:
Evolution of cellular automata using instruction-based approach. IEEE Congress on Evolutionary Computation 2012: 1-8 - [c25]Lukás Sekanina, Vojtech Salajka, Zdenek Vasícek:
Two-step evolution of polymorphic circuits for image multi-filtering. IEEE Congress on Evolutionary Computation 2012: 1-8 - [c24]Zdenek Vasícek, Lukás Sekanina:
On area minimization of complex combinational circuits using cartesian genetic programming. IEEE Congress on Evolutionary Computation 2012: 1-8 - [c23]Lukás Sekanina, Zdenek Vasícek:
A SAT-based fitness function for evolutionary optimization of polymorphic circuits. DATE 2012: 715-720 - [c22]Zdenek Vasícek, Karel Slaný:
Efficient Phenotype Evaluation in Cartesian Genetic Programming. EuroGP 2012: 266-278 - 2011
- [j1]Zdenek Vasícek, Lukás Sekanina:
Formal verification of candidate solutions for post-synthesis evolutionary optimization in evolvable hardware. Genet. Program. Evolvable Mach. 12(3): 305-327 (2011) - [c21]Zdenek Vasícek, Michal Bidlo, Lukás Sekanina, Kyrre Glette:
Evolutionary design of efficient and robust switching image filters. AHS 2011: 192-199 - [c20]Zdenek Vasícek, Michal Bidlo:
Evolutionary design of robust noise-specific image filters. IEEE Congress on Evolutionary Computation 2011: 269-276 - [c19]Zdenek Vasícek, Lukás Sekanina:
A global postsynthesis optimization method for combinational circuits. DATE 2011: 1525-1528 - [p1]Lukás Sekanina, Zdenek Vasícek:
CGP Acceleration Using Field-Programmable Gate Arrays. Cartesian Genetic Programming 2011: 217-230 - 2010
- [c18]Zdenek Vasícek, Lukás Sekanina, Michal Bidlo:
A method for design of impulse bursts noise filters optimized for FPGA implementations. DATE 2010: 1731-1736 - [c17]Petr Fiser, Jan Schmidt, Zdenek Vasícek, Lukás Sekanina:
On logic synthesis of conventionally hard to synthesize circuits using genetic programming. DDECS 2010: 346-351 - [c16]Michal Bidlo, Zdenek Vasícek, Karel Slaný:
Sorting Network Development Using Cellular Automata. ICES 2010: 85-96
2000 – 2009
- 2009
- [c15]Zdenek Vasícek, Michal Bidlo, Lukás Sekanina, Jim Tørresen, Kyrre Glette, Marcus Furuholmen:
Evolution of Impulse Bursts Noise Filters. AHS 2009: 27-34 - [c14]Michal Bidlo, Zdenek Vasícek:
Comparison of the Uniform and Non-Uniform Cellular Automata-Based Approach to the Development of Combinational Circuits. AHS 2009: 423-430 - [c13]Michal Bidlo, Zdenek Vasícek:
Investigating gate-level evolutionary development of combinational multipliers using enhanced cellular automata-based model. IEEE Congress on Evolutionary Computation 2009: 2241-2248 - [c12]Michal Bidlo, Zdenek Vasícek:
Development of combinational circuits using non-uniform cellular automata: initial results. GECCO 2009: 1839-1840 - [c11]Lukás Sekanina, Richard Ruzicka, Zdenek Vasícek, Roman Prokop, Lukás Fujcik:
REPOMO32 - New reconfigurable polymorphic integrated circuit for adaptive hardware. WEAH 2009: 39-46 - 2008
- [c10]Zdenek Vasícek, Ladislav Capka, Lukás Sekanina:
Analysis of Reconfiguration Options for a Reconfigurable Polymorphic Circuit. AHS 2008: 3-10 - [c9]Michal Bidlo, Zdenek Vasícek:
Gate-Level Evolutionary Development Using Cellular Automata. AHS 2008: 11-18 - [c8]Zdenek Vasícek, Lukás Sekanina:
Novel Hardware Implementation of Adaptive Median Filters. DDECS 2008: 110-115 - [c7]Zdenek Vasícek, Lukás Sekanina:
Hardware Accelerators for Cartesian Genetic Programming. EuroGP 2008: 230-241 - [c6]Michal Bidlo, Zdenek Vasícek:
Cellular Automata-Based Development of Combinational and Polymorphic Circuits: A Comparative Study. ICES 2008: 106-117 - [c5]Zdenek Vasícek, Martin Zádník, Lukás Sekanina, Jirí Tobola:
On Evolutionary Synthesis of Linear Transforms in FPGA. ICES 2008: 141-152 - 2007
- [c4]Zdenek Vasícek, Lukás Sekanina:
Evaluation of a New Platform For Image Filter Evolution. AHS 2007: 577-586 - [c3]Zdenek Vasícek, Lukás Sekanina:
An area-efficient alternative to adaptive median filtering in FPGAs. FPL 2007: 216-221 - [c2]Zdenek Vasícek, Lukás Sekanina:
Reducing the Area on a Chip Using a Bank of Evolved Filters. ICES 2007: 222-232 - 2006
- [c1]Lukás Sekanina, Zdenek Vasícek:
On the Practical Limits of the Evolutionary Digital Filter Design at the Gate Level. EvoWorkshops 2006: 344-355
Coauthor Index
[c78] [c77] [i11] [j16] [c74] [i9] [j15] [j13] [j12] [j10] [c69] [c68] [c67] [c66] [i8] [i7] [i6] [i5] [c64] [c63] [c60] [p3] [i3] [i2] [i1] [j7] [c58] [c57] [c55] [c54] [c53] [c52] [c51] [c49] [c48] [j5] [c46] [c45] [c43] [j4] [c39] [c38] [c37] [p2] [c36] [c35] [c34] [c31] [j3] [j2] [c29] [c25] [c24] [c23] [j1] [c21] [c19] [p1] [c18] [c17] [c15] [c11] [c10] [c8] [c7] [c5] [c4] [c3] [c2] [c1]
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