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ORCID25th VLSI Design 2012: Hyderabad, India
- Vishwani D. Agrawal, Srimat T. Chakradhar:
25th International Conference on VLSI Design, Hyderabad, India, January 7-11, 2012. IEEE Computer Society 2012, ISBN 978-1-4673-0438-2 - Vishwani D. Agrawal:
Keynote Talk: A History of the VLSI Design Conference. 1-2 - Jaswinder S. Ahuja:
Keynote Talk: Semiconductor Industry: Best of Times, Worst of Times, and Nowhere Else I Would Rather Be! 3-4 - Bert Gyselinckx:
Keynote Talk: A Wireless Sensor a Day Keeps the Doctor Away. 5-6 - Rajesh Gupta:
Keynote Talk: The Variability Expeditions: Exploring the Software Stack for Underdesigned Computing Machines. 7-8 - Samarjit Chakraborty:
Keynote Talk: Challenges in Automotive Cyber-physical Systems Design. 9-10 - Sumit Adhikari, Markus Damm, Christoph Grimm, François Pêcheux:
Tutorial T1: Design of Mixed-Signal Systems using SystemC AMS Extensions. 11-12 - Himanshu Thapliyal, Nagarajan Ranganathan:
Tutorial T2: Reversible Logic: Fundamentals and Applications in Ultra-Low Power, Fault Testing and Emerging Nanotechnologies, and Challenges in Future. 13-15 - Srikanth Venkataraman, Nagesh Tamarapalli:
Tutorial T3: DFM, DFT, Silicon Debug and Diagnosis - The Loop to Ensure Product Yield. 16-17 - Susmita Sur-Kolay, Swarup Bhunia:
Tutorial T4: Intellectual Property Protection and Security in System-on-Chip Design. 18-19 - Pavan Kumar Hanumolu, Un-Ku Moon, Terri S. Fiez:
Tutorial T5: Advanced Analog-Mixed Signal System and Circuit Techniques. 20-21 - Nikil D. Dutt
, Mani B. Srivastava, Rajesh Gupta, Subhasish Mitra:
Tutorial T6: Variability-resistant Software and Hardware for Nano-Scale Computing. 22-24 - David Atienza, Arvind Sridhar:
Tutorial T7A: New Modeling Methodologies for Thermal Analysis of 3D ICs and Advanced Cooling Technologies of the Future. 25-26 - Shankar Hemmady:
Tutorial T7B: Optimally Addressing Verification Constraint Complexity for Effective Functional Convergence. 27 - Ajay Joshi:
Tutorial T8A: Designing Silicon-Photonic Communication Networks for Manycore Systems. 28 - B. Kameswara Rao, Muralidhar Reddy B., Ravi Kishore B.:
Tutorial T8B: Wireless System Design and Systems Engineering Challenges. 29-30 - Annajirao Garimella, Punith R. Surkanti, Paul M. Furth:
Embedded Tutorial ET1: Pole-Zero Analysis of Low-Dropout (LDO) Regulators: A Tutorial Overview. 31-32 - M. Kalyana Kumar Rao, Shantha Kumari P. V., Boopalan Sellappan:
Embedded Tutorial ET2: Digital Subscriber Line. 33-34 - Siva Kothamasu:
Embedded Tutorial ET3: Packaging Trends, Die Package Co-Design Flow and Challenges. 35 - Vijay Raghunathan:
Embedded Tutorial ET4: Advanced Techniques for Programming Networked Embedded Systems. 36-37 - Sathyam K. Pattanam, P. P. Chakrabarti, Mahesh Mahendale, Srikanth Jadcherla, Seer Akademi, Vikas Gautham, Raju Bala Showry Pudota:
Panel Discussion: SoC Realization - A Bridge to New Horizons or a Bridge to Nowhere? 38 - Nilanjan Chattaraj, Anindya Sundar Dhar:
Random Access Analog Memory (RA2M) for Video Signal Application. 39-44 - Manas Kumar Hati, Tarun Kanti Bhattacharyya:
A 55-mW 300MS/s 8-bit CMOS Parallel Pipeline ADC. 45-50 - Saravana Kumar, Shouri Chatterjee:
A 110-dB Dynamic Range, 76-dB Peak SNR Companding Continuous-Time ?S Modulator for Audio Applications. 51-56 - Supriya Aggarwal, Kavita Khare:
Hardware Efficient Architecture for Generating Sine/Cosine Waves. 57-61 - Rajesh A. Patil, Gauri Gupta, Vineet Sahula, Atanendu S. Mandal:
Power Aware Hardware Prototyping of Multiclass SVM Classifier Through Reconfiguration. 62-67 - S. K. Sahoo, K. Srinivasa Reddy:
A High Speed FIR Filter Architecture Based on Novel Higher Radix Algorithm. 68-73 - Warin Sootkaneung, Kewal K. Saluja:
Impact of Body Bias Based Leakage Power Reduction on Soft Error Rate. 74-79 - Ankur Goel, Donald Evans, Richard Stephani, Venkateswara Reddy, Dharmendra Rai, Veerabadra Chary, N. Sathisha:
An Area Efficient Diode and On Transistor Interchangeable Power Gating Scheme with Trim Options for Low Power SRAMs. 80-84 - Amitava Ghosh, Isha Das, Achintya Halder:
An Energy Efficient Oscillator Frequency Calibration Methodology Using Fraction Phase Computation. 85-91 - Nitin Gupta, Tapas Nandy, Phalguni Bala:
Self-Induced Supply Noise Reduction Technique in GBPS Rate Transmitters. 92-95 - Mohit Singh, Shalabh Gupta:
Buffer Design and Eye-Diagram Based Characterization of a 20 GS/s CMOS DAC. 96-100 - Pawan Kumar Moyade, Nandakumar Nambath, Allmin Ansari, Shalabh Gupta:
Analog Processing Based Equalizer for 40 Gbps Coherent Optical Links in 90 nm CMOS. 101-106 - Jimit Shah, K. S. Raghunandan, Kuruvilla Varghese:
HD Resolution Intra Prediction Architecture for H.264 Decoder. 107-112 - Bodhisatwa Mazumdar, Debdeep Mukhopadhyay, Indranil Sengupta:
Design for Security of Block Cipher S-Boxes to Resist Differential Power Attacks. 113-118 - Prateek Verma, Preeti Rao:
Real-time Melodic Accompaniment System for Indian Music Using TMS320C6713. 119-124 - Sujan K. Manohar, Vinod K. Somasundar, Ramakrishnan Venkatasubramanian, Poras T. Balsara:
Bidirectional Single-Supply Level Shifter with Wide Voltage Range for Efficient Power Management. 125-130 - Annajirao Garimella, Punith R. Surkanti, Paul M. Furth:
Pole-Zero Analysis of Low-Dropout (LDO) Regulators: A Tutorial Overview. 131-136 - Vinayak Honkote, Ankit More, Baris Taskin:
3-D Parasitic Modeling for Rotary Interconnects. 137-142 - Debashis Banerjee, Shreyas Sen, Shyam Kumar Devarakond, Abhijit Chatterjee:
Power Aware Post-Manufacture Tuning of MIMO Receiver Systems. 143-148 - Dhiraj Reddy Nallapa Yoge, Nitin Chandrachoodan:
GPU Implementation of a Programmable Turbo Decoder for Software Defined Radio Applications. 149-154 - Junyoung Park, H. Mert Ustun, Jacob A. Abraham:
Run-time Prediction of the Optimal Performance Point in DVS-based Dynamic Thermal Management. 155-160 - Zhe Wang, Sanjay Ranka, Prabhat Mishra:
Temperature-aware Task Partitioning for Real-Time Scheduling in Embedded Systems. 161-166 - Cory E. Merkel, Dhireesha Kudithipudi:
Towards Thermal Profiling in CMOS/Memristor Hybrid RRAM Architectures. 167-172 - Pramod Murali, Navakanta Bhat, Gaurab Banerjee, Bharadwaj Amrutur, K. N. Bhat, Praveen C. Ramamurthy:
CMOS Gas Sensor Array Platform with Fourier Transform Based Impedance Spectroscopy. 173-178 - Subhajit Sen, Dan Babitch, Noshir Dubash:
A Compact Temperature Sensor at 1.8µA per Hz Conversion Rate and 1.1 °C Accuracy for SOCs. 179-184 - Anindya Lal Roy, Anirban Bhattacharya, Ritesh Ray Chaudhuri, Tarun Kanti Bhattacharyya:
Analysis of the Pull-In Phenomenon in Microelectromechanical Varactors. 185-190 - Jean-Michel Chabloz, Ahmed Hemani:
Low-Latency No-Handshake GALS Interfaces for Fast-Receiver Links. 191-196 - Ankit Kagliwal, Shankar Balachandran:
Set-Cover Heuristics for Two-Level Logic Minimization. 197-202 - Liang Tang, Jorgen Peddersen, Sri Parameswaran:
A Rapid Methodology for Multi-mode Communication Circuit Generation. 203-208 - Mahima Arrawatia, Varish Diddi, Harsha Kochar, Maryam Shojaei Baghini, Girish Kumar:
An Integrated CMOS RF Energy Harvester with Differential Microstrip Antenna and On-Chip Charger. 209-214 - Chao Lu, Sang Phill Park, Vijay Raghunathan, Kaushik Roy:
Low-Overhead Maximum Power Point Tracking for Micro-Scale Solar Energy Harvesting Systems. 215-220 - Sujan K. Manohar, Ramakrishnan Venkatasubramanian, Poras T. Balsara:
Hybrid NEMS-CMOS DC-DC Converter for Improved Area and Power Efficiency. 221-226 - Ritwik Mukherjee, Hafizur Rahaman, Indrajit Banerjee, Tuhina Samanta, Parthasarathi Dasgupta:
A Heuristic Method for Co-optimization of Pin Assignment and Droplet Routing in Digital Microfluidic Biochip. 227-232 - Pinaki Chakrabarti:
Clock Tree Skew Minimization with Structured Routing. 233-237 - Sourindra Chaudhuri, Prateek Mishra, Niraj K. Jha:
Accurate Leakage Estimation for FinFET Standard Cells Using the Response Surface Methodology. 238-244 - Joshua W. Wells, Jayaram Natarajan, Abhijit Chatterjee, Irtaza Barlas:
Real-Time, Content Aware Camera - Algorithm - Hardware Co-Adaptation for Minimal Power Video Encoding. 245-250 - C. J. Janraj, T. Venkata Kalyan, Tripti S. Warrier, Madhu Mutyam:
Way Sharing Set Associative Cache Architecture. 251-256 - Deepa N. Sarma, Gopalakrishnan Lakshminarayanan, K. V. R. Suryakiran Chavali:
A Novel Encoding Scheme for Low Power in Network on Chip Links. 257-261 - Nishit Ashok Kapadia, Sudeep Pasricha:
A Power Delivery Network Aware Framework for Synthesis of 3D Networks-on-Chip with Multiple Voltage Islands. 262-267 - Sudeep Pasricha:
A Framework for TSV Serialization-aware Synthesis of Application Specific 3D Networks-on-Chip. 268-273 - Deepak Kumar Meher, Arunkumar Salimath, Achintya Halder:
An Ultra-low Power Symbol Detection Methodology and Its Circuit Implementation for a Wake-up Receiver in Wireless Sensor Nodes. 274-279 - Chetan Vudadha, Goutham Makkena, M. Venkata Swamy Nayudu, P. Sai Phaneendra, Syed Ershad Ahmed, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, M. B. Srinivas:
Low-Power Self Reconfigurable Multiplexer Based Decoder for Adaptive Resolution Flash ADCs. 280-285 - Raguram Damodaran, Timothy Anderson, Sanjive Agarwala, Rama Venkatasubramanian, Michael Gill, Dhileep Gopalakrishnan, Anthony M. Hill, Abhijeet Chachad, Dheera Balasubramanian, Naveen Bhoria, Jonathan Tran, Duc Bui, Mujibur Rahman, Shriram Moharil, Matthew Pierson, Steven Mullinnix, Hung Ong, David Thompson, Krishna Gurram, Oluleye Olorode, Nuruddin Mahmood, Jose Flores, Arjun Rajagopal, Soujanya Narnur, Daniel Wu, Alan Hales, Kyle Peavy, Robert Sussman:
A 1.25GHz 0.8W C66x DSP Core in 40nm CMOS. 286-291 - Praveen Salihundam, Mohammed Asadullah Khan, Shailendra Jain, Yatin Vasant Hoskote, Satish Yada, Shasi Kumar, Vasantha Erraguntla, Sriram R. Vangal, Nitin Borkar:
A Reconfigurable On-die Traffic Generator in 45nm CMOS for a 48 iA-32 Core Network-on-Chip. 292-297 - Somnath Banerjee, Tushar Gupta:
Efficient Online RTL Debugging Methodology for Logic Emulation Systems. 298-303 - Xinmu Wang, Seetharam Narasimhan, Aswin Raghav Krishna, Swarup Bhunia:
SCARE: Side-Channel Analysis Based Reverse Engineering for Post-Silicon Validation. 304-309 - Oghenekarho Okobiah, Saraju P. Mohanty, Elias Kougianos, Oleg Garitselov:
Kriging-Assisted Ultra-Fast Simulated-Annealing Optimization of a Clamped Bitline Sense Amplifier. 310-315 - Oleg Garitselov, Saraju P. Mohanty, Elias Kougianos:
Fast-Accurate Non-Polynomial Metamodeling for Nano-CMOS PLL Design Optimization. 316-321 - Angada B. Sachid, Pallavi Paliwal, S. Joshi, Maryam Shojaei Baghini, Dinesh Sharma, V. Ramgopal Rao:
Circuit Optimization at 22nm Technology Node. 322-327 - Kamalika Datta, Gaurav Rathi, Indranil Sengupta, Hafizur Rahaman:
Synthesis of Reversible Circuits Using Heuristic Search Method. 328-333 - Sajib Kumar Mitra, Ahsan Raja Chowdhury:
Minimum Cost Fault Tolerant Adder Circuits in Reversible Logic Synthesis. 334-339 - Lei Wang, Somnath Paul, Swarup Bhunia:
Width-Aware Fine-Grained Dynamic Supply Gating: A Design Methodology for Low-Power Datapath and Memory. 340-345 - Ozgur Sinanoglu:
Eliminating Performance Penalty of Scan. 346-351 - Srinivas Vooka, Khushboo Agarwal, Abhijeet Shrivastava, Pranav Murthy, Ramakrishnan Venkatraman:
A Silicon Testing Strategy for Pulse-Width Failures. 352-357 - Arvind Jain, Maheedhar Jalasutram, Srinivas Vooka, Prasun Nair, Neeraj Pradhan:
At-speed Testing of Asynchronous Reset De-assertion Faults. 358-363 - Debjit Pal, Pallab Dasgupta, Siddhartha Mukhopadhyay:
A Library for Passive Online Verification of Analog and Mixed-Signal Circuits. 364-369 - Supriyo Maji, Pradip Mandal:
A Fast Equation Free Iterative Approach to Analog Circuit Sizing. 370-375 - Samiran Dam, Pradip Mandal:
Iterative Performance Model Upgradation in Geometric Programming Based Analog Circuit Sizing for Improved Design Accuracy. 376-381 - Matthias Sauer, Stefan Kupferschmid, Alejandro Czutro, Sudhakar M. Reddy, Bernd Becker:
Analysis of Reachable Sensitisable Paths in Sequential Circuits with SAT and Craig Interpolation. 382-387 - Jinpeng Lv, Priyank Kalla:
Formal Verification of Galois Field Multipliers Using Computer Algebra Techniques. 388-393 - Sarvesh Prabhu, Michael S. Hsiao, Loganathan Lingappan, Vijay Gangaram:
A Novel SMT-Based Technique for LFSR Reseeding. 394-399 - Yogesh Dilip Save, H. Narayanan, Sachin B. Patkar:
Two Graph Based Circuit Simulator for PDE-Electrical Analogy. 400-405 - Tarun Kumar Agarwal, Mamidala Jagadesh Kumar:
Modeling of Partially Depleted SOI DEMOSFETs with a Sub-circuit Utilizing the HiSIM-HV Compact Model. 406-411 - H. C. Srinivasaiah:
Implications of Halo Implant Shadowing and Backscattering from Mask Layer Edges on Device Leakage Current in 65nm SRAM. 412-417 - Unmesh D. Bordoloi, Bharath Suri, Swaroop Nunna, Samarjit Chakraborty, Petru Eles, Zebo Peng:
Customizing Instruction Set Extensible Reconfigurable Processors Using GPUs. 418-423 - Anandaroop Ghosh, Somnath Paul, Swarup Bhunia:
Energy-Efficient Application Mapping in FPGA through Computation in Embedded Memory Blocks. 424-429 - Hadi Hajimiri, Prabhat Mishra:
Intra-Task Dynamic Cache Reconfiguration. 430-435 - Subhadip Kundu, Santanu Chattopadhyay, Indranil Sengupta, Rohit Kapur:
A Diagnosability Metric for Test Set Selection Targeting Better Fault Detection. 436-441 - Breeta SenGupta, Urban Ingelsson, Erik Larsson:
Test Planning for Core-based 3D Stacked ICs with Through-Silicon Vias. 442-447 - Priyadharshini Shanmugasundaram, Vishwani D. Agrawal:
Externally Tested Scan Circuit with Built-In Activity Monitor and Adaptive Test Clock. 448-453
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