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ORCIDSheqin Dong
- > Home > Persons > Sheqin Dong
Publications
- 2011
[j20]Kan Wang
, Sheqin Dong, Yuchun Ma, Yu Wang, Xianlong Hong, Jason Cong:
Leakage-Aware TSV-Planning with Power-Temperature-Delay Dependence in 3D ICs. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 94-A(12): 2490-2498 (2011)- [c64]Kan Wang, Yuchun Ma, Sheqin Dong, Yu Wang, Xianlong Hong, Jason Cong:
Rethinking thermal via planning with timing-power-temperature dependence for 3D ICs. ASP-DAC 2011: 261-266 - 2009
- [c54]Sheqin Dong, Hongjie Bai, Xianlong Hong, Satoshi Goto:
Buffer Planning for 3D ICs. ISCAS 2009: 1735-1738 - [c53]Xu He, Sheqin Dong, Yuchun Ma, Xianlong Hong:
Simultaneous buffer and interlayer via planning for 3D floorplanning. ISQED 2009: 740-745 - [c52]Xu He, Sheqin Dong, Xianlong Hong, Satoshi Goto:
Integrated interlayer via planning and pin assignment for 3D ICs. SLIP 2009: 99-104 - 2008
- [c51]Xin Li, Yuchun Ma, Xianlong Hong, Sheqin Dong, Jason Cong:
LP based white space redistribution for thermal via planning and performance optimization in 3D ICs. ASP-DAC 2008: 209-212 - [c50]Jiayi Liu, Sheqin Dong, Xianlong Hong, Yibo Wang, Ou He, Satoshi Goto:
Symmetry constraint based on mismatch analysis for analog layout in SOI technology. ASP-DAC 2008: 772-775 - 2007
- [j13]Yaoguang Wei, Sheqin Dong, Xianlong Hong:
APWL-Y: An accurate and efficient wirelength estimation technique for hexagon/triangle placement. Integr. 40(4): 406-419 (2007) - [c45]Jiayi Liu, Sheqin Dong, Yuchun Ma, Di Long, Xianlong Hong:
Thermal-driven Symmetry Constraint for Analog Layout with CBL Representation. ASP-DAC 2007: 191-196 - [c44]Yuchun Ma, Zhuoyuan Li, Jason Cong, Xianlong Hong, Glenn Reinman, Sheqin Dong, Qiang Zhou:
Micro-architecture Pipelining Optimization with Throughput-Aware Floorplanning. ASP-DAC 2007: 920-925 - [c42]Ou He, Sheqin Dong, Jinian Bian, Yuchun Ma, Xianlong Hong:
An effective buffer planning algorithm for IP based fixed-outline SOC placement. ACM Great Lakes Symposium on VLSI 2007: 564-569 - [c41]Lingyi Zhang, Sheqin Dong, Xianlong Hong, Yuchun Ma:
A Fast 3D-BSG Algorithm for 3D Packing Problem. ISCAS 2007: 2044-2047 - [c40]Hongjie Bai, Sheqin Dong, Xianlong Hong:
Congestion Driven Buffer Planning for X-Architecture. ISQED 2007: 835-840 - [c39]Liu Yang, Sheqin Dong, Yuchun Ma, Xianlong Hong:
Interconnect Power Optimization Based on Timing Analysis. ISVLSI 2007: 119-124 - [c38]Yaoguang Wei, Sheqin Dong, Xianlong Hong, Yuchun Ma:
An accurate and efficient probabilistic congestion estimation model in x architecture. SLIP 2007: 25-32 - 2006
- [j12]Yuchun Ma, Xianlong Hong, Sheqin Dong, Chung-Kuan Cheng, Jun Gu:
General Floorplans with L/T-Shaped Blocks Using Corner Block List. J. Comput. Sci. Technol. 21(6): 922-926 (2006) - [j11]Song Chen, Sheqin Dong, Xianlong Hong, Yuchun Ma, Chung-Kuan Cheng:
VLSI Block Placement With Alignment Constraints. IEEE Trans. Circuits Syst. II Express Briefs 53-II(8): 622-626 (2006) - [c37]Liu Yang, Sheqin Dong, Xianlong Hong, Yuchun Ma:
A Two-stage Incremental Floorplanning Algorithm with Boundary Constraints. APCCAS 2006: 792-795 - [c36]Di Long, Xianlong Hong, Sheqin Dong:
Signal-path driven partition and placement for analog circuit. ASP-DAC 2006: 694-699 - [c35]Hongjie Bai, Sheqin Dong, Xianlong Hong, Song Chen:
Buffer planning based on block exchanging. ISCAS 2006 - [c34]Sheqin Dong, Shuyi Zheng, Xianlong Hong:
Floorplanning for 2.5-D system integration using multi-layer-BSG structure. ISCAS 2006 - [c33]Shaojun Wei, Sheqin Dong, Xianlong Hong, Youliang Wu:
On handling the fixed-outline constraints of floorplanning using less flexibility first principles. ISCAS 2006 - [c32]Sheqin Dong, Fan Guo, Jun Yuan, Rensheng Wang, Xianlong Hong:
A Novel Tour Construction Heuristic for Traveling Salesman Problem Using LFF Principle. JCIS 2006 - [c31]Sheqin Dong, Fan Guo, Jun Yuan, Rensheng Wang, Xianlong Hong:
Stochastic Local Search Using the Search Space Smoothing Meta-Heuristic: A Case Study. JCIS 2006 - [c30]Sheqin Dong, Rensheng Wang, Fan Guo, Jun Yuan, Xianlong Hong:
Floorplanning by A Revised 3-D Corner Block List with sub-C+-tree. JCIS 2006 - 2005
- [j10]Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Chung-Kuan Cheng, Jun Gu:
Buffer planning as an Integral part of floorplanning with consideration of routing congestion. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(4): 609-621 (2005) - [c28]Renshen Wang, Sheqin Dong, Xianlong Hong:
An improved P-admissible floorplan representation based on Corner Block List. ASP-DAC 2005: 1115-1118 - [c27]Jun Yuan, Sheqin Dong, Xianlong Hong, Yuliang Wu:
LFF algorithm for heterogeneous FPGA floorplanning. ASP-DAC 2005: 1123-1126 - [c26]Rong Liu, Sheqin Dong, Xianlong Hong:
An efficient algorithm to fixed-outline floorplanning based on instance augmentation. CAD/Graphics 2005: 6 - [c25]Hongjie Bai, Sheqin Dong, Xianlong Hong, Song Chen:
A New Buffer Planning Algorithm Based on Room Resizing. EUC 2005: 291-299 - [c24]Rong Liu, Sheqin Dong, Xianlong Hong:
Fixed-outline floorplanning based on common subsequence. ACM Great Lakes Symposium on VLSI 2005: 156-159 - [c23]Zhe Zhou, Sheqin Dong, Xianlong Hong, Yuliang Wu, Yoji Kajitani:
A new approach based on LFF for optimization of dynamic hardware reconfigurations. ISCAS (2) 2005: 1210-1213 - [c22]Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Chung-Kuan Cheng:
Performance constrained floorplanning based on partial clustering [IC layout]. ISCAS (2) 2005: 1863-1866 - [c21]Rong Liu, Sheqin Dong, Xianlong Hong, Yoji Kajitani:
Fixed-outline floorplanning with constraints through instance augmentation. ISCAS (2) 2005: 1883-1886 - [c20]Di Long, Xianlong Hong, Sheqin Dong:
Optimal two-dimension common centroid layout generation for MOS transistors unit-circuit. ISCAS (3) 2005: 2999-3002 - [c19]Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Chung-Kuan Cheng:
VLSI block placement with alignment constraints based on corner block list. ISCAS (6) 2005: 6222-6225 - [c18]Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Chung-Kuan Cheng:
Buffer Planning Algorithm Based on Partial Clustered Floorplanning. ISQED 2005: 213-219 - [c17]Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Chung-Kuan Cheng:
Floorplanning with Consideration of White Space Resource Distribution for Repeater Planning. ISQED 2005: 628-633 - 2004
- [j9]Xianlong Hong, Yuchun Ma, Sheqin Dong, Yici Cai, Chung-Kuan Cheng, Jun Gu:
Corner block list representation and its application with boundary constraints. Sci. China Ser. F Inf. Sci. 47(1): 1-19 (2004) - [j8]Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Yici Cai, Chung-Kuan Cheng, Jun Gu:
A buffer planning algorithm for chip-level floorplanning. Sci. China Ser. F Inf. Sci. 47(6): 763-776 (2004) - [j7]Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Chung-Kuan Cheng, Jun Gu:
Fast Evaluation of Bounded Slice-Line Grid. J. Comput. Sci. Technol. 19(6): 973-980 (2004) - [j6]Xianlong Hong, Sheqin Dong, Gang Huang, Yici Cai, Chung-Kuan Cheng, Jun Gu:
Corner block list representation and its application to floorplan optimization. IEEE Trans. Circuits Syst. II Express Briefs 51-II(5): 228-233 (2004) - [j5]Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Chung-Kuan Cheng, Jun Gu:
Stairway compaction using corner block list and its applications with rectilinear blocks. ACM Trans. Design Autom. Electr. Syst. 9(2): 199-211 (2004) - [c16]Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Yici Cai, Chung-Kuan Cheng, Jun Gu:
A buffer planning algorithm with congestion optimization. ASP-DAC 2004: 615-620 - [c15]Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Yici Cai, Chung-Kuan Cheng, Jun Gu:
Buffer allocation algorithm with consideration of routing congestion. ASP-DAC 2004: 621-623 - [c14]Sheqin Dong, Zhong Yang, Xianlong Hong, Yuliang Wu:
Module placement based on quadratic programming and rectangle packing using less flexibility first principle. ISCAS (5) 2004: 61-64 - 2003
- [j4]Sheqin Dong, Xianlong Hong, Song Chen, Xin Qi, Ruijie Wang, Jun Gu:
VLSI Module Placement with Pre-Placed Modules and with Consideration of Congestion Using Solution Space Smoothing. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 86-A(12): 3136-3147 (2003) - [j3]Sheqin Dong, Xianlong Hong, Yuliang Wu, Jun Gu:
Deterministic VLSI Block Placement Algorithm Using Less Flexibility First Principle. J. Comput. Sci. Technol. 18(6): 739-746 (2003) - [c13]Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Yici Cai, Chung-Kuan Cheng, Jun Gu:
A buffer planning algorithm based on dead space redistribution. ASP-DAC 2003: 435-438 - [c12]Sheqin Dong, Xianlong Hong, Xin Qi, Ruijie Wang, Song Chen, Jun Gu:
VLSI module placement with pre-placed modules and considering congestion using solution space smoothing. ASP-DAC 2003: 741-744 - [c11]Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Yici Cai, Chung-Kuan Cheng, Jun Gu:
Dynamic global buffer planning optimization based on detail block locating and congestion analysis. DAC 2003: 806-811 - [c10]Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Song Chen, Chung-Kuan Cheng, Jun Gu:
Arbitrary convex and concave rectilinear block packing based on corner block list. ISCAS (5) 2003: 493-496 - [c9]Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Yici Cai, Chung-Kuan Cheng, Jun Gu:
Evaluating a bounded slice-line grid assignment in O(nlogn) time. ISCAS (4) 2003: 708-711 - [c8]Rui Liu, Sheqin Dong, Xianlong Hong, Di Long, Jun Gu:
Algorithms for analog VLSI 2D stack generation and block merging. ISCAS (4) 2003: 716-719 - [c7]Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Yici Cai, Chung-Kuan Cheng, Jun Gu:
An integrated floorplanning with an efficient buffer planning algorithm. ISPD 2003: 136-142 - 2002
- [j2]Sheqin Dong, Shuo Zhou, Xianlong Hong, Chung-Kuan Cheng, Jun Gu, Yici Cai:
An Optimum Placement Search Algorithm Based on Extended Corner Block List. J. Comput. Sci. Technol. 17(6): 699-707 (2002) - [c6]Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Chung-Kuan Cheng, Jun Gu:
Stairway Compaction using Corner Block List and Its Applications with Rectilinear Blocks. ASP-DAC/VLSI Design 2002: 387-392 - 2001
- [j1]Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Chung-Kuan Cheng, Jun Gu:
Floorplanning with abutment constraints based on corner block list. Integr. 31(1): 65-77 (2001) - [c5]Yuchun Ma, Sheqin Dong, Xianlong Hong, Yici Cai, Chung-Kuan Cheng, Jun Gu:
VLSI floorplanning with boundary constraints based on corner block list. ASP-DAC 2001: 509-514 - [c4]Sheqin Dong, Xianlong Hong, Youliang Wu, Yizhou Lin, Jun Gu:
VLSI block placement using less flexibility first principles. ASP-DAC 2001: 601-604 - [c3]Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Chung-Kuan Cheng, Jun Gu:
Floorplanning with Abutment Constraints and L-Shaped/T-Shaped Blocks based on Corner Block List. DAC 2001: 770-775 - 2000
- [c1]Xianlong Hong, Gang Huang, Yici Cai, Jiangchun Gu, Sheqin Dong, Chung-Kuan Cheng, Jun Gu:
Corner Block List: An Effective and Efficient Topological Representation of Non-Slicing Floorplan. ICCAD 2000: 8-12
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